edma3_rl_cc.h

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/******************************************************************************
**+-------------------------------------------------------------------------+**
**|                            ****                                         |**
**|                            ****                                         |**
**|                            ******o***                                   |**
**|                      ********_///_****                                  |**
**|                      ***** /_//_/ ****                                  |**
**|                       ** ** (__/ ****                                   |**
**|                           *********                                     |**
**|                            ****                                         |**
**|                            ***                                          |**
**|                                                                         |**
**|         Copyright (c) 1998-2006 Texas Instruments Incorporated          |**
**|                        ALL RIGHTS RESERVED                              |**
**|                                                                         |**
**| Permission is hereby granted to licensees of Texas Instruments          |**
**| Incorporated (TI) products to use this computer program for the sole    |**
**| purpose of implementing a licensee product based on TI products.        |**
**| No other rights to reproduce, use, or disseminate this computer         |**
**| program, whether in part or in whole, are granted.                      |**
**|                                                                         |**
**| TI makes no representation or warranties with respect to the            |**
**| performance of this computer program, and specifically disclaims        |**
**| any responsibility for any damages, special or consequential,           |**
**| connected with the use of this program.                                 |**
**|                                                                         |**
**+-------------------------------------------------------------------------+**
******************************************************************************/

/**  \file   edma3_rl_cc.h
       \brief  EDMA3 Channel Controller Register Desciption.

        This file contains the register layer for the EDMA3 Channel Controller.

    (C) Copyright 2006, Texas Instruments, Inc

    \version
                1.0     Anuj Aggarwal       - Created

 */

#ifndef _EDMA3_RL_CC_H_
#define _EDMA3_RL_CC_H_

#ifdef __cplusplus
extern "C" {
#endif

/**************************************************************************\
* Register Overlay Structure for DRA
\**************************************************************************/
typedef struct  {
    volatile unsigned int DRAE;
    volatile unsigned int DRAEH;
} EDMA3_CCRL_DraRegs;

/**************************************************************************\
* Register Overlay Structure for QUEEVTENTRY
\**************************************************************************/
typedef struct  {
    volatile unsigned int QUEEVT_ENTRY;
} EDMA3_CCRL_QueevtentryRegs;

/**************************************************************************\
* Register Overlay Structure for SHADOW
\**************************************************************************/
typedef struct  {
    volatile unsigned int ER;
    volatile unsigned int ERH;
    volatile unsigned int ECR;
    volatile unsigned int ECRH;
    volatile unsigned int ESR;
    volatile unsigned int ESRH;
    volatile unsigned int CER;
    volatile unsigned int CERH;
    volatile unsigned int EER;
    volatile unsigned int EERH;
    volatile unsigned int EECR;
    volatile unsigned int EECRH;
    volatile unsigned int EESR;
    volatile unsigned int EESRH;
    volatile unsigned int SER;
    volatile unsigned int SERH;
    volatile unsigned int SECR;
    volatile unsigned int SECRH;
    volatile unsigned char RSVD0[8];
    volatile unsigned int IER;
    volatile unsigned int IERH;
    volatile unsigned int IECR;
    volatile unsigned int IECRH;
    volatile unsigned int IESR;
    volatile unsigned int IESRH;
    volatile unsigned int IPR;
    volatile unsigned int IPRH;
    volatile unsigned int ICR;
    volatile unsigned int ICRH;
    volatile unsigned int IEVAL;
    volatile unsigned char RSVD1[4];
    volatile unsigned int QER;
    volatile unsigned int QEER;
    volatile unsigned int QEECR;
    volatile unsigned int QEESR;
    volatile unsigned int QSER;
    volatile unsigned int QSECR;
    volatile unsigned char RSVD2[360];
} EDMA3_CCRL_ShadowRegs;

typedef volatile EDMA3_CCRL_ShadowRegs  *EDMA3_CCRL_ShadowRegsOvly;

/**************************************************************************\
* Register Overlay Structure for PARAMENTRY
\**************************************************************************/
typedef struct  {
    volatile unsigned int OPT;
    volatile unsigned int SRC;
    volatile unsigned int A_B_CNT;
    volatile unsigned int DST;
    volatile unsigned int SRC_DST_BIDX;
    volatile unsigned int LINK_BCNTRLD;
    volatile unsigned int SRC_DST_CIDX;
    volatile unsigned int CCNT;
} EDMA3_CCRL_ParamentryRegs;
typedef volatile EDMA3_CCRL_ParamentryRegs  *EDMA3_CCRL_ParamentryRegsOvly;

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile unsigned int REV;
    volatile unsigned int CCCFG;
    volatile unsigned char RSVD0[248];
    volatile unsigned int DCHMAP[64];
    volatile unsigned int QCHMAP[8];
    volatile unsigned char RSVD1[32];
    volatile unsigned int DMAQNUM[8];
    volatile unsigned int QDMAQNUM;
    volatile unsigned char RSVD2[28];
    volatile unsigned int QUETCMAP;
    volatile unsigned int QUEPRI;
    volatile unsigned char RSVD3[120];
    volatile unsigned int EMR;
    volatile unsigned int EMRH;
    volatile unsigned int EMCR;
    volatile unsigned int EMCRH;
    volatile unsigned int QEMR;
    volatile unsigned int QEMCR;
    volatile unsigned int CCERR;
    volatile unsigned int CCERRCLR;
    volatile unsigned int EEVAL;
    volatile unsigned char RSVD4[28];
    EDMA3_CCRL_DraRegs DRA[8];
    volatile unsigned int QRAE[8];
    volatile unsigned char RSVD5[96];
    EDMA3_CCRL_QueevtentryRegs QUEEVTENTRY[8][16];
    volatile unsigned int QSTAT[8];
    volatile unsigned int QWMTHRA;
    volatile unsigned int QWMTHRB;
    volatile unsigned char RSVD6[24];
    volatile unsigned int CCSTAT;
    volatile unsigned char RSVD7[188];
    volatile unsigned int AETCTL;
    volatile unsigned int AETSTAT;
    volatile unsigned int AETCMD;
    volatile unsigned char RSVD8[244];
    volatile unsigned int MPFAR;
    volatile unsigned int MPFSR;
    volatile unsigned int MPFCR;
    volatile unsigned int MPPAG;
    volatile unsigned int MPPA[8];
    volatile unsigned char RSVD9[2000];
    volatile unsigned int ER;
    volatile unsigned int ERH;
    volatile unsigned int ECR;
    volatile unsigned int ECRH;
    volatile unsigned int ESR;
    volatile unsigned int ESRH;
    volatile unsigned int CER;
    volatile unsigned int CERH;
    volatile unsigned int EER;
    volatile unsigned int EERH;
    volatile unsigned int EECR;
    volatile unsigned int EECRH;
    volatile unsigned int EESR;
    volatile unsigned int EESRH;
    volatile unsigned int SER;
    volatile unsigned int SERH;
    volatile unsigned int SECR;
    volatile unsigned int SECRH;
    volatile unsigned char RSVD10[8];
    volatile unsigned int IER;
    volatile unsigned int IERH;
    volatile unsigned int IECR;
    volatile unsigned int IECRH;
    volatile unsigned int IESR;
    volatile unsigned int IESRH;
    volatile unsigned int IPR;
    volatile unsigned int IPRH;
    volatile unsigned int ICR;
    volatile unsigned int ICRH;
    volatile unsigned int IEVAL;
    volatile unsigned char RSVD11[4];
    volatile unsigned int QER;
    volatile unsigned int QEER;
    volatile unsigned int QEECR;
    volatile unsigned int QEESR;
    volatile unsigned int QSER;
    volatile unsigned int QSECR;
    volatile unsigned char RSVD12[3944];
    EDMA3_CCRL_ShadowRegs SHADOW[8];
    volatile unsigned char RSVD13[4096];
    EDMA3_CCRL_ParamentryRegs PARAMENTRY[512];
} EDMA3_CCRL_Regs;

typedef volatile EDMA3_CCRL_Regs  *EDMA3_CCRL_RegsOvly;


/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* REV */

#define EDMA3_CCRL_REV_TYPE_MASK         (0x00FF0000u)
#define EDMA3_CCRL_REV_TYPE_SHIFT        (0x00000010u)
#define EDMA3_CCRL_REV_TYPE_RESETVAL     (0x00000007u)

#define EDMA3_CCRL_REV_CLASS_MASK        (0x0000FF00u)
#define EDMA3_CCRL_REV_CLASS_SHIFT       (0x00000008u)
#define EDMA3_CCRL_REV_CLASS_RESETVAL    (0x00000004u)

#define EDMA3_CCRL_REV_RESERVED_MASK     (0x000000FFu)
#define EDMA3_CCRL_REV_RESERVED_SHIFT    (0x00000000u)
#define EDMA3_CCRL_REV_RESERVED_RESETVAL (0x00000000u)

#define EDMA3_CCRL_REV_RESETVAL          (0x00070400u)

/* CCCFG */

#define EDMA3_CCRL_CCCFG_MP_EXIST_MASK   (0x02000000u)
#define EDMA3_CCRL_CCCFG_MP_EXIST_SHIFT  (0x00000019u)
#define EDMA3_CCRL_CCCFG_MP_EXIST_RESETVAL (0x00000000u)

/*----MP_EXIST Tokens----*/
#define EDMA3_CCRL_CCCFG_MP_EXIST_NONE   (0x00000000u)
#define EDMA3_CCRL_CCCFG_MP_EXIST_INCLUDED (0x00000001u)

#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_MASK (0x01000000u)
#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_SHIFT (0x00000018u)
#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_RESETVAL (0x00000000u)

/*----CHMAP_EXIST Tokens----*/
#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_NONE (0x00000000u)
#define EDMA3_CCRL_CCCFG_CHMAP_EXIST_INCLUDED (0x00000001u)

#define EDMA3_CCRL_CCCFG_NUM_REGN_MASK   (0x00300000u)
#define EDMA3_CCRL_CCCFG_NUM_REGN_SHIFT  (0x00000014u)
#define EDMA3_CCRL_CCCFG_NUM_REGN_RESETVAL (0x00000000u)

/*----NUM_REGN Tokens----*/
#define EDMA3_CCRL_CCCFG_NUM_REGN_0      (0x00000000u)
#define EDMA3_CCRL_CCCFG_NUM_REGN_2      (0x00000001u)
#define EDMA3_CCRL_CCCFG_NUM_REGN_4      (0x00000002u)
#define EDMA3_CCRL_CCCFG_NUM_REGN_8      (0x00000003u)

#define EDMA3_CCRL_CCCFG_NUM_TC_MASK     (0x00070000u)
#define EDMA3_CCRL_CCCFG_NUM_TC_SHIFT    (0x00000010u)
#define EDMA3_CCRL_CCCFG_NUM_TC_RESETVAL (0x00000000u)

/*----NUM_TC Tokens----*/
#define EDMA3_CCRL_CCCFG_NUM_TC_1        (0x00000000u)
#define EDMA3_CCRL_CCCFG_NUM_TC_2        (0x00000001u)
#define EDMA3_CCRL_CCCFG_NUM_TC_3        (0x00000002u)
#define EDMA3_CCRL_CCCFG_NUM_TC_4        (0x00000003u)
#define EDMA3_CCRL_CCCFG_NUM_TC_5        (0x00000004u)
#define EDMA3_CCRL_CCCFG_NUM_TC_6        (0x00000005u)
#define EDMA3_CCRL_CCCFG_NUM_TC_7        (0x00000006u)
#define EDMA3_CCRL_CCCFG_NUM_TC_8        (0x00000007u)

#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_MASK (0x00007000u)
#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_SHIFT (0x0000000Cu)
#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_RESETVAL (0x00000000u)

/*----NUM_PAENTRY Tokens----*/
#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_16  (0x00000000u)
#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_32  (0x00000001u)
#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_64  (0x00000002u)
#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_128 (0x00000003u)
#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_256 (0x00000004u)
#define EDMA3_CCRL_CCCFG_NUM_PAENTRY_512 (0x00000005u)

#define EDMA3_CCRL_CCCFG_NUM_INTCH_MASK  (0x00000700u)
#define EDMA3_CCRL_CCCFG_NUM_INTCH_SHIFT (0x00000008u)
#define EDMA3_CCRL_CCCFG_NUM_INTCH_RESETVAL (0x00000000u)

/*----NUM_INTCH Tokens----*/
#define EDMA3_CCRL_CCCFG_NUM_INTCH_8     (0x00000001u)
#define EDMA3_CCRL_CCCFG_NUM_INTCH_16    (0x00000002u)
#define EDMA3_CCRL_CCCFG_NUM_INTCH_32    (0x00000003u)
#define EDMA3_CCRL_CCCFG_NUM_INTCH_64    (0x00000004u)

#define EDMA3_CCRL_CCCFG_NUM_QDMACH_MASK (0x00000070u)
#define EDMA3_CCRL_CCCFG_NUM_QDMACH_SHIFT (0x00000004u)
#define EDMA3_CCRL_CCCFG_NUM_QDMACH_RESETVAL (0x00000000u)

/*----NUM_QDMACH Tokens----*/
#define EDMA3_CCRL_CCCFG_NUM_QDMACH_NONE (0x00000000u)
#define EDMA3_CCRL_CCCFG_NUM_QDMACH_2    (0x00000001u)
#define EDMA3_CCRL_CCCFG_NUM_QDMACH_4    (0x00000002u)
#define EDMA3_CCRL_CCCFG_NUM_QDMACH_6    (0x00000003u)
#define EDMA3_CCRL_CCCFG_NUM_QDMACH_8    (0x00000004u)

#define EDMA3_CCRL_CCCFG_NUM_DMACH_MASK  (0x00000007u)
#define EDMA3_CCRL_CCCFG_NUM_DMACH_SHIFT (0x00000000u)
#define EDMA3_CCRL_CCCFG_NUM_DMACH_RESETVAL (0x00000000u)

/*----NUM_DMACH Tokens----*/
#define EDMA3_CCRL_CCCFG_NUM_DMACH_NONE  (0x00000000u)
#define EDMA3_CCRL_CCCFG_NUM_DMACH_4     (0x00000001u)
#define EDMA3_CCRL_CCCFG_NUM_DMACH_8     (0x00000002u)
#define EDMA3_CCRL_CCCFG_NUM_DMACH_16    (0x00000003u)
#define EDMA3_CCRL_CCCFG_NUM_DMACH_32    (0x00000004u)
#define EDMA3_CCRL_CCCFG_NUM_DMACH_64    (0x00000005u)
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