edma3_rl_cc.h

来自「vicp做为dm6446上的硬件加速器」· C头文件 代码 · 共 1,607 行 · 第 1/5 页

#define EDMA3_CCRL_DRAE_E6_MASK          (0x00000040u)
#define EDMA3_CCRL_DRAE_E6_SHIFT         (0x00000006u)
#define EDMA3_CCRL_DRAE_E6_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_DRAE_E5_MASK          (0x00000020u)
#define EDMA3_CCRL_DRAE_E5_SHIFT         (0x00000005u)
#define EDMA3_CCRL_DRAE_E5_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_DRAE_E4_MASK          (0x00000010u)
#define EDMA3_CCRL_DRAE_E4_SHIFT         (0x00000004u)
#define EDMA3_CCRL_DRAE_E4_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_DRAE_E3_MASK          (0x00000008u)
#define EDMA3_CCRL_DRAE_E3_SHIFT         (0x00000003u)
#define EDMA3_CCRL_DRAE_E3_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_DRAE_E2_MASK          (0x00000004u)
#define EDMA3_CCRL_DRAE_E2_SHIFT         (0x00000002u)
#define EDMA3_CCRL_DRAE_E2_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_DRAE_E1_MASK          (0x00000002u)
#define EDMA3_CCRL_DRAE_E1_SHIFT         (0x00000001u)
#define EDMA3_CCRL_DRAE_E1_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_DRAE_E0_MASK          (0x00000001u)
#define EDMA3_CCRL_DRAE_E0_SHIFT         (0x00000000u)
#define EDMA3_CCRL_DRAE_E0_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_DRAE_RESETVAL         (0x00000000u)

/* DRAEH */

#define EDMA3_CCRL_DRAEH_E63_MASK        (0x80000000u)
#define EDMA3_CCRL_DRAEH_E63_SHIFT       (0x0000001Fu)
#define EDMA3_CCRL_DRAEH_E63_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E62_MASK        (0x40000000u)
#define EDMA3_CCRL_DRAEH_E62_SHIFT       (0x0000001Eu)
#define EDMA3_CCRL_DRAEH_E62_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E61_MASK        (0x20000000u)
#define EDMA3_CCRL_DRAEH_E61_SHIFT       (0x0000001Du)
#define EDMA3_CCRL_DRAEH_E61_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E60_MASK        (0x10000000u)
#define EDMA3_CCRL_DRAEH_E60_SHIFT       (0x0000001Cu)
#define EDMA3_CCRL_DRAEH_E60_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E59_MASK        (0x08000000u)
#define EDMA3_CCRL_DRAEH_E59_SHIFT       (0x0000001Bu)
#define EDMA3_CCRL_DRAEH_E59_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E58_MASK        (0x04000000u)
#define EDMA3_CCRL_DRAEH_E58_SHIFT       (0x0000001Au)
#define EDMA3_CCRL_DRAEH_E58_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E57_MASK        (0x02000000u)
#define EDMA3_CCRL_DRAEH_E57_SHIFT       (0x00000019u)
#define EDMA3_CCRL_DRAEH_E57_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E56_MASK        (0x01000000u)
#define EDMA3_CCRL_DRAEH_E56_SHIFT       (0x00000018u)
#define EDMA3_CCRL_DRAEH_E56_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E55_MASK        (0x00800000u)
#define EDMA3_CCRL_DRAEH_E55_SHIFT       (0x00000017u)
#define EDMA3_CCRL_DRAEH_E55_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E54_MASK        (0x00400000u)
#define EDMA3_CCRL_DRAEH_E54_SHIFT       (0x00000016u)
#define EDMA3_CCRL_DRAEH_E54_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E53_MASK        (0x00200000u)
#define EDMA3_CCRL_DRAEH_E53_SHIFT       (0x00000015u)
#define EDMA3_CCRL_DRAEH_E53_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E52_MASK        (0x00100000u)
#define EDMA3_CCRL_DRAEH_E52_SHIFT       (0x00000014u)
#define EDMA3_CCRL_DRAEH_E52_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E51_MASK        (0x00080000u)
#define EDMA3_CCRL_DRAEH_E51_SHIFT       (0x00000013u)
#define EDMA3_CCRL_DRAEH_E51_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E50_MASK        (0x00040000u)
#define EDMA3_CCRL_DRAEH_E50_SHIFT       (0x00000012u)
#define EDMA3_CCRL_DRAEH_E50_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E49_MASK        (0x00020000u)
#define EDMA3_CCRL_DRAEH_E49_SHIFT       (0x00000011u)
#define EDMA3_CCRL_DRAEH_E49_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E48_MASK        (0x00010000u)
#define EDMA3_CCRL_DRAEH_E48_SHIFT       (0x00000010u)
#define EDMA3_CCRL_DRAEH_E48_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E47_MASK        (0x00008000u)
#define EDMA3_CCRL_DRAEH_E47_SHIFT       (0x0000000Fu)
#define EDMA3_CCRL_DRAEH_E47_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E46_MASK        (0x00004000u)
#define EDMA3_CCRL_DRAEH_E46_SHIFT       (0x0000000Eu)
#define EDMA3_CCRL_DRAEH_E46_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E45_MASK        (0x00002000u)
#define EDMA3_CCRL_DRAEH_E45_SHIFT       (0x0000000Du)
#define EDMA3_CCRL_DRAEH_E45_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E44_MASK        (0x00001000u)
#define EDMA3_CCRL_DRAEH_E44_SHIFT       (0x0000000Cu)
#define EDMA3_CCRL_DRAEH_E44_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E43_MASK        (0x00000800u)
#define EDMA3_CCRL_DRAEH_E43_SHIFT       (0x0000000Bu)
#define EDMA3_CCRL_DRAEH_E43_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E42_MASK        (0x00000400u)
#define EDMA3_CCRL_DRAEH_E42_SHIFT       (0x0000000Au)
#define EDMA3_CCRL_DRAEH_E42_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E41_MASK        (0x00000200u)
#define EDMA3_CCRL_DRAEH_E41_SHIFT       (0x00000009u)
#define EDMA3_CCRL_DRAEH_E41_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E40_MASK        (0x00000100u)
#define EDMA3_CCRL_DRAEH_E40_SHIFT       (0x00000008u)
#define EDMA3_CCRL_DRAEH_E40_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E39_MASK        (0x00000080u)
#define EDMA3_CCRL_DRAEH_E39_SHIFT       (0x00000007u)
#define EDMA3_CCRL_DRAEH_E39_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E38_MASK        (0x00000040u)
#define EDMA3_CCRL_DRAEH_E38_SHIFT       (0x00000006u)
#define EDMA3_CCRL_DRAEH_E38_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E37_MASK        (0x00000020u)
#define EDMA3_CCRL_DRAEH_E37_SHIFT       (0x00000005u)
#define EDMA3_CCRL_DRAEH_E37_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E36_MASK        (0x00000010u)
#define EDMA3_CCRL_DRAEH_E36_SHIFT       (0x00000004u)
#define EDMA3_CCRL_DRAEH_E36_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E35_MASK        (0x00000008u)
#define EDMA3_CCRL_DRAEH_E35_SHIFT       (0x00000003u)
#define EDMA3_CCRL_DRAEH_E35_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E34_MASK        (0x00000004u)
#define EDMA3_CCRL_DRAEH_E34_SHIFT       (0x00000002u)
#define EDMA3_CCRL_DRAEH_E34_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E33_MASK        (0x00000002u)
#define EDMA3_CCRL_DRAEH_E33_SHIFT       (0x00000001u)
#define EDMA3_CCRL_DRAEH_E33_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_E32_MASK        (0x00000001u)
#define EDMA3_CCRL_DRAEH_E32_SHIFT       (0x00000000u)
#define EDMA3_CCRL_DRAEH_E32_RESETVAL    (0x00000000u)

#define EDMA3_CCRL_DRAEH_RESETVAL        (0x00000000u)

/* QRAE */

#define EDMA3_CCRL_QRAE_E7_MASK          (0x00000080u)
#define EDMA3_CCRL_QRAE_E7_SHIFT         (0x00000007u)
#define EDMA3_CCRL_QRAE_E7_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_QRAE_E6_MASK          (0x00000080u)
#define EDMA3_CCRL_QRAE_E6_SHIFT         (0x00000007u)
#define EDMA3_CCRL_QRAE_E6_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_QRAE_E5_MASK          (0x00000080u)
#define EDMA3_CCRL_QRAE_E5_SHIFT         (0x00000007u)
#define EDMA3_CCRL_QRAE_E5_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_QRAE_E4_MASK          (0x00000080u)
#define EDMA3_CCRL_QRAE_E4_SHIFT         (0x00000007u)
#define EDMA3_CCRL_QRAE_E4_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_QRAE_E3_MASK          (0x00000080u)
#define EDMA3_CCRL_QRAE_E3_SHIFT         (0x00000007u)
#define EDMA3_CCRL_QRAE_E3_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_QRAE_E2_MASK          (0x00000080u)
#define EDMA3_CCRL_QRAE_E2_SHIFT         (0x00000007u)
#define EDMA3_CCRL_QRAE_E2_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_QRAE_E1_MASK          (0x00000080u)
#define EDMA3_CCRL_QRAE_E1_SHIFT         (0x00000007u)
#define EDMA3_CCRL_QRAE_E1_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_QRAE_E0_MASK          (0x00000080u)
#define EDMA3_CCRL_QRAE_E0_SHIFT         (0x00000007u)
#define EDMA3_CCRL_QRAE_E0_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_QRAE_RESERVED_MASK    (0x0000007Fu)
#define EDMA3_CCRL_QRAE_RESERVED_SHIFT   (0x00000000u)
#define EDMA3_CCRL_QRAE_RESERVED_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QRAE_RESETVAL         (0x00000000u)

/* QUEEVT_ENTRY */

#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_MASK (0xFFFFFF00u)
#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_SHIFT (0x00000008u)
#define EDMA3_CCRL_QUEEVT_ENTRY_RESV_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_MASK (0x000000C0u)
#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_SHIFT (0x00000006u)
#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_MASK (0x0000003Fu)
#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SHIFT (0x00000000u)
#define EDMA3_CCRL_QUEEVT_ENTRY_EVT_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEEVT_ENTRY_RESETVAL (0x00000000u)

/* QSTAT */

#define EDMA3_CCRL_QSTAT_THRXD_MASK      (0x01000000u)
#define EDMA3_CCRL_QSTAT_THRXD_SHIFT     (0x00000018u)
#define EDMA3_CCRL_QSTAT_THRXD_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QSTAT_RESERVED_MASK   (0x00600000u)
#define EDMA3_CCRL_QSTAT_RESERVED_SHIFT  (0x00000015u)
#define EDMA3_CCRL_QSTAT_RESERVED_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QSTAT_WM_MASK         (0x001F0000u)
#define EDMA3_CCRL_QSTAT_WM_SHIFT        (0x00000010u)
#define EDMA3_CCRL_QSTAT_WM_RESETVAL     (0x00000000u)

#define EDMA3_CCRL_QSTAT_NUMVAL_MASK     (0x00001F00u)
#define EDMA3_CCRL_QSTAT_NUMVAL_SHIFT    (0x00000008u)
#define EDMA3_CCRL_QSTAT_NUMVAL_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QSTAT_STRTPTR_MASK    (0x0000000Fu)
#define EDMA3_CCRL_QSTAT_STRTPTR_SHIFT   (0x00000000u)
#define EDMA3_CCRL_QSTAT_STRTPTR_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QSTAT_RESETVAL        (0x00000000u)

/* QWMTHRA */

#define EDMA3_CCRL_QWMTHRA_Q3_MASK       (0x1F000000u)
#define EDMA3_CCRL_QWMTHRA_Q3_SHIFT      (0x00000018u)
#define EDMA3_CCRL_QWMTHRA_Q3_RESETVAL   (0x00000010u)

#define EDMA3_CCRL_QWMTHRA_Q2_MASK       (0x001F0000u)
#define EDMA3_CCRL_QWMTHRA_Q2_SHIFT      (0x00000010u)
#define EDMA3_CCRL_QWMTHRA_Q2_RESETVAL   (0x00000010u)

#define EDMA3_CCRL_QWMTHRA_Q1_MASK       (0x00001F00u)
#define EDMA3_CCRL_QWMTHRA_Q1_SHIFT      (0x00000008u)
#define EDMA3_CCRL_QWMTHRA_Q1_RESETVAL   (0x00000010u)

#define EDMA3_CCRL_QWMTHRA_Q0_MASK       (0x0000001Fu)
#define EDMA3_CCRL_QWMTHRA_Q0_SHIFT      (0x00000000u)
#define EDMA3_CCRL_QWMTHRA_Q0_RESETVAL   (0x00000010u)

#define EDMA3_CCRL_QWMTHRA_RESETVAL      (0x10101010u)

/* QWMTHRB */

#define EDMA3_CCRL_QWMTHRB_Q7_MASK       (0x1F000000u)
#define EDMA3_CCRL_QWMTHRB_Q7_SHIFT      (0x00000018u)
#define EDMA3_CCRL_QWMTHRB_Q7_RESETVAL   (0x00000010u)

#define EDMA3_CCRL_QWMTHRB_Q6_MASK       (0x001F0000u)
#define EDMA3_CCRL_QWMTHRB_Q6_SHIFT      (0x00000010u)
#define EDMA3_CCRL_QWMTHRB_Q6_RESETVAL   (0x00000010u)

#define EDMA3_CCRL_QWMTHRB_Q5_MASK       (0x00001F00u)
#define EDMA3_CCRL_QWMTHRB_Q5_SHIFT      (0x00000008u)
#define EDMA3_CCRL_QWMTHRB_Q5_RESETVAL   (0x00000010u)

#define EDMA3_CCRL_QWMTHRB_Q4_MASK       (0x0000001Fu)
#define EDMA3_CCRL_QWMTHRB_Q4_SHIFT      (0x00000000u)
#define EDMA3_CCRL_QWMTHRB_Q4_RESETVAL   (0x00000010u)

#define EDMA3_CCRL_QWMTHRB_RESETVAL      (0x10101010u)

/* CCSTAT */

#define EDMA3_CCRL_CCSTAT_QUEACTV7_MASK  (0x00800000u)
#define EDMA3_CCRL_CCSTAT_QUEACTV7_SHIFT (0x00000017u)
#define EDMA3_CCRL_CCSTAT_QUEACTV7_RESETVAL (0x00000000u)

/*----QUEACTV7 Tokens----*/
#define EDMA3_CCRL_CCSTAT_QUEACTV7_NONE  (0x00000000u)
#define EDMA3_CCRL_CCSTAT_QUEACTV7_ACTIVE (0x00000001u)

#define EDMA3_CCRL_CCSTAT_QUEACTV6_MASK  (0x00400000u)
#define EDMA3_CCRL_CCSTAT_QUEACTV6_SHIFT (0x00000016u)
#define EDMA3_CCRL_CCSTAT_QUEACTV6_RESETVAL (0x00000000u)

/*----QUEACTV6 Tokens----*/
#define EDMA3_CCRL_CCSTAT_QUEACTV6_NONE  (0x00000000u)
#define EDMA3_CCRL_CCSTAT_QUEACTV6_ACTIVE (0x00000001u)

#define EDMA3_CCRL_CCSTAT_QUEACTV5_MASK  (0x00200000u)
#define EDMA3_CCRL_CCSTAT_QUEACTV5_SHIFT (0x00000015u)
#define EDMA3_CCRL_CCSTAT_QUEACTV5_RESETVAL (0x00000000u)

/*----QUEACTV5 Tokens----*/
#define EDMA3_CCRL_CCSTAT_QUEACTV5_NONE  (0x00000000u)
#define EDMA3_CCRL_CCSTAT_QUEACTV5_ACTIVE (0x00000001u)

#define EDMA3_CCRL_CCSTAT_QUEACTV4_MASK  (0x00100000u)
#define EDMA3_CCRL_CCSTAT_QUEACTV4_SHIFT (0x00000014u)
#define EDMA3_CCRL_CCSTAT_QUEACTV4_RESETVAL (0x00000000u)

/*----QUEACTV4 Tokens----*/
#define EDMA3_CCRL_CCSTAT_QUEACTV4_NONE  (0x00000000u)
#define EDMA3_CCRL_CCSTAT_QUEACTV4_ACTIVE (0x00000001u)

#define EDMA3_CCRL_CCSTAT_QUEACTV3_MASK  (0x00080000u)
#define EDMA3_CCRL_CCSTAT_QU