edma3_rl_cc.h

来自「vicp做为dm6446上的硬件加速器」· C头文件 代码 · 共 1,607 行 · 第 1/5 页

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#define EDMA3_CCRL_CCCFG_RESETVAL        (0x00000000u)

/* DCHMAP */

#define EDMA3_CCRL_DCHMAP_PAENTRY_MASK   (0x00003FE0u)
#define EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT  (0x00000005u)
#define EDMA3_CCRL_DCHMAP_PAENTRY_RESETVAL (0x00000000u)

#define EDMA3_CCRL_DCHMAP_RESETVAL       (0x00000000u)

/* QCHMAP */

#define EDMA3_CCRL_QCHMAP_PAENTRY_MASK   (0x00003FE0u)
#define EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT  (0x00000005u)
#define EDMA3_CCRL_QCHMAP_PAENTRY_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QCHMAP_TRWORD_MASK    (0x0000001Cu)
#define EDMA3_CCRL_QCHMAP_TRWORD_SHIFT   (0x00000002u)
#define EDMA3_CCRL_QCHMAP_TRWORD_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QCHMAP_RESETVAL       (0x00000000u)

/* DMAQNUM */

#define EDMA3_CCRL_DMAQNUM_E7_MASK       (0x70000000u)
#define EDMA3_CCRL_DMAQNUM_E7_SHIFT      (0x0000001Cu)
#define EDMA3_CCRL_DMAQNUM_E7_RESETVAL   (0x00000000u)

#define EDMA3_CCRL_DMAQNUM_E6_MASK       (0x07000000u)
#define EDMA3_CCRL_DMAQNUM_E6_SHIFT      (0x00000018u)
#define EDMA3_CCRL_DMAQNUM_E6_RESETVAL   (0x00000000u)

#define EDMA3_CCRL_DMAQNUM_E5_MASK       (0x00700000u)
#define EDMA3_CCRL_DMAQNUM_E5_SHIFT      (0x00000014u)
#define EDMA3_CCRL_DMAQNUM_E5_RESETVAL   (0x00000000u)

#define EDMA3_CCRL_DMAQNUM_E4_MASK       (0x00070000u)
#define EDMA3_CCRL_DMAQNUM_E4_SHIFT      (0x00000010u)
#define EDMA3_CCRL_DMAQNUM_E4_RESETVAL   (0x00000000u)

#define EDMA3_CCRL_DMAQNUM_E3_MASK       (0x00007000u)
#define EDMA3_CCRL_DMAQNUM_E3_SHIFT      (0x0000000Cu)
#define EDMA3_CCRL_DMAQNUM_E3_RESETVAL   (0x00000000u)

#define EDMA3_CCRL_DMAQNUM_E2_MASK       (0x00000700u)
#define EDMA3_CCRL_DMAQNUM_E2_SHIFT      (0x00000008u)
#define EDMA3_CCRL_DMAQNUM_E2_RESETVAL   (0x00000000u)

#define EDMA3_CCRL_DMAQNUM_E1_MASK       (0x00000070u)
#define EDMA3_CCRL_DMAQNUM_E1_SHIFT      (0x00000004u)
#define EDMA3_CCRL_DMAQNUM_E1_RESETVAL   (0x00000000u)

#define EDMA3_CCRL_DMAQNUM_E0_MASK       (0x00000007u)
#define EDMA3_CCRL_DMAQNUM_E0_SHIFT      (0x00000000u)
#define EDMA3_CCRL_DMAQNUM_E0_RESETVAL   (0x00000000u)

#define EDMA3_CCRL_DMAQNUM_RESETVAL      (0x00000000u)

/* QDMAQNUM */

#define EDMA3_CCRL_QDMAQNUM_E7_MASK      (0x70000000u)
#define EDMA3_CCRL_QDMAQNUM_E7_SHIFT     (0x0000001Cu)
#define EDMA3_CCRL_QDMAQNUM_E7_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QDMAQNUM_E6_MASK      (0x07000000u)
#define EDMA3_CCRL_QDMAQNUM_E6_SHIFT     (0x00000018u)
#define EDMA3_CCRL_QDMAQNUM_E6_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QDMAQNUM_E5_MASK      (0x00700000u)
#define EDMA3_CCRL_QDMAQNUM_E5_SHIFT     (0x00000014u)
#define EDMA3_CCRL_QDMAQNUM_E5_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QDMAQNUM_E4_MASK      (0x00070000u)
#define EDMA3_CCRL_QDMAQNUM_E4_SHIFT     (0x00000010u)
#define EDMA3_CCRL_QDMAQNUM_E4_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QDMAQNUM_E3_MASK      (0x00007000u)
#define EDMA3_CCRL_QDMAQNUM_E3_SHIFT     (0x0000000Cu)
#define EDMA3_CCRL_QDMAQNUM_E3_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QDMAQNUM_E2_MASK      (0x00000700u)
#define EDMA3_CCRL_QDMAQNUM_E2_SHIFT     (0x00000008u)
#define EDMA3_CCRL_QDMAQNUM_E2_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QDMAQNUM_E1_MASK      (0x00000070u)
#define EDMA3_CCRL_QDMAQNUM_E1_SHIFT     (0x00000004u)
#define EDMA3_CCRL_QDMAQNUM_E1_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QDMAQNUM_E0_MASK      (0x00000007u)
#define EDMA3_CCRL_QDMAQNUM_E0_SHIFT     (0x00000000u)
#define EDMA3_CCRL_QDMAQNUM_E0_RESETVAL  (0x00000000u)

#define EDMA3_CCRL_QDMAQNUM_RESETVAL     (0x00000000u)

/* QUETCMAP */

#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_MASK (0x70000000u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_SHIFT (0x0000001Cu)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ7_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_MASK (0x07000000u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_SHIFT (0x00000018u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ6_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_MASK (0x00700000u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_SHIFT (0x00000014u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ5_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_MASK (0x00070000u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_SHIFT (0x00000010u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ4_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_MASK (0x00007000u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_SHIFT (0x0000000Cu)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ3_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_MASK (0x00000700u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_SHIFT (0x00000008u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ2_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_MASK (0x00000070u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_SHIFT (0x00000004u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ1_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_MASK (0x00000007u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_SHIFT (0x00000000u)
#define EDMA3_CCRL_QUETCMAP_TCNUMQ0_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUETCMAP_RESETVAL     (0x00000000u)

/* QUEPRI */

#define EDMA3_CCRL_QUEPRI_PRIQ7_MASK     (0x70000000u)
#define EDMA3_CCRL_QUEPRI_PRIQ7_SHIFT    (0x0000001Cu)
#define EDMA3_CCRL_QUEPRI_PRIQ7_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEPRI_PRIQ6_MASK     (0x07000000u)
#define EDMA3_CCRL_QUEPRI_PRIQ6_SHIFT    (0x00000018u)
#define EDMA3_CCRL_QUEPRI_PRIQ6_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEPRI_PRIQ5_MASK     (0x00700000u)
#define EDMA3_CCRL_QUEPRI_PRIQ5_SHIFT    (0x00000014u)
#define EDMA3_CCRL_QUEPRI_PRIQ5_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEPRI_PRIQ4_MASK     (0x00070000u)
#define EDMA3_CCRL_QUEPRI_PRIQ4_SHIFT    (0x00000010u)
#define EDMA3_CCRL_QUEPRI_PRIQ4_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEPRI_PRIQ3_MASK     (0x00007000u)
#define EDMA3_CCRL_QUEPRI_PRIQ3_SHIFT    (0x0000000Cu)
#define EDMA3_CCRL_QUEPRI_PRIQ3_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEPRI_PRIQ2_MASK     (0x00000700u)
#define EDMA3_CCRL_QUEPRI_PRIQ2_SHIFT    (0x00000008u)
#define EDMA3_CCRL_QUEPRI_PRIQ2_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEPRI_PRIQ1_MASK     (0x00000070u)
#define EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT    (0x00000004u)
#define EDMA3_CCRL_QUEPRI_PRIQ1_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEPRI_PRIQ0_MASK     (0x00000007u)
#define EDMA3_CCRL_QUEPRI_PRIQ0_SHIFT    (0x00000000u)
#define EDMA3_CCRL_QUEPRI_PRIQ0_RESETVAL (0x00000000u)

#define EDMA3_CCRL_QUEPRI_RESETVAL       (0x00000000u)

/* EMR */

#define EDMA3_CCRL_EMR_E31_MASK          (0x80000000u)
#define EDMA3_CCRL_EMR_E31_SHIFT         (0x0000001Fu)
#define EDMA3_CCRL_EMR_E31_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E30_MASK          (0x40000000u)
#define EDMA3_CCRL_EMR_E30_SHIFT         (0x0000001Eu)
#define EDMA3_CCRL_EMR_E30_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E29_MASK          (0x20000000u)
#define EDMA3_CCRL_EMR_E29_SHIFT         (0x0000001Du)
#define EDMA3_CCRL_EMR_E29_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E28_MASK          (0x10000000u)
#define EDMA3_CCRL_EMR_E28_SHIFT         (0x0000001Cu)
#define EDMA3_CCRL_EMR_E28_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E27_MASK          (0x08000000u)
#define EDMA3_CCRL_EMR_E27_SHIFT         (0x0000001Bu)
#define EDMA3_CCRL_EMR_E27_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E26_MASK          (0x04000000u)
#define EDMA3_CCRL_EMR_E26_SHIFT         (0x0000001Au)
#define EDMA3_CCRL_EMR_E26_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E25_MASK          (0x02000000u)
#define EDMA3_CCRL_EMR_E25_SHIFT         (0x00000019u)
#define EDMA3_CCRL_EMR_E25_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E24_MASK          (0x01000000u)
#define EDMA3_CCRL_EMR_E24_SHIFT         (0x00000018u)
#define EDMA3_CCRL_EMR_E24_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E23_MASK          (0x00800000u)
#define EDMA3_CCRL_EMR_E23_SHIFT         (0x00000017u)
#define EDMA3_CCRL_EMR_E23_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E22_MASK          (0x00400000u)
#define EDMA3_CCRL_EMR_E22_SHIFT         (0x00000016u)
#define EDMA3_CCRL_EMR_E22_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E21_MASK          (0x00200000u)
#define EDMA3_CCRL_EMR_E21_SHIFT         (0x00000015u)
#define EDMA3_CCRL_EMR_E21_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E20_MASK          (0x00100000u)
#define EDMA3_CCRL_EMR_E20_SHIFT         (0x00000014u)
#define EDMA3_CCRL_EMR_E20_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E19_MASK          (0x00080000u)
#define EDMA3_CCRL_EMR_E19_SHIFT         (0x00000013u)
#define EDMA3_CCRL_EMR_E19_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E18_MASK          (0x00040000u)
#define EDMA3_CCRL_EMR_E18_SHIFT         (0x00000012u)
#define EDMA3_CCRL_EMR_E18_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E17_MASK          (0x00020000u)
#define EDMA3_CCRL_EMR_E17_SHIFT         (0x00000011u)
#define EDMA3_CCRL_EMR_E17_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E16_MASK          (0x00010000u)
#define EDMA3_CCRL_EMR_E16_SHIFT         (0x00000010u)
#define EDMA3_CCRL_EMR_E16_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E15_MASK          (0x00008000u)
#define EDMA3_CCRL_EMR_E15_SHIFT         (0x0000000Fu)
#define EDMA3_CCRL_EMR_E15_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E14_MASK          (0x00004000u)
#define EDMA3_CCRL_EMR_E14_SHIFT         (0x0000000Eu)
#define EDMA3_CCRL_EMR_E14_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E13_MASK          (0x00002000u)
#define EDMA3_CCRL_EMR_E13_SHIFT         (0x0000000Du)
#define EDMA3_CCRL_EMR_E13_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E12_MASK          (0x00001000u)
#define EDMA3_CCRL_EMR_E12_SHIFT         (0x0000000Cu)
#define EDMA3_CCRL_EMR_E12_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E11_MASK          (0x00000800u)
#define EDMA3_CCRL_EMR_E11_SHIFT         (0x0000000Bu)
#define EDMA3_CCRL_EMR_E11_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E10_MASK          (0x00000400u)
#define EDMA3_CCRL_EMR_E10_SHIFT         (0x0000000Au)
#define EDMA3_CCRL_EMR_E10_RESETVAL      (0x00000000u)

#define EDMA3_CCRL_EMR_E9_MASK           (0x00000200u)
#define EDMA3_CCRL_EMR_E9_SHIFT          (0x00000009u)
#define EDMA3_CCRL_EMR_E9_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E8_MASK           (0x00000100u)
#define EDMA3_CCRL_EMR_E8_SHIFT          (0x00000008u)
#define EDMA3_CCRL_EMR_E8_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E7_MASK           (0x00000080u)
#define EDMA3_CCRL_EMR_E7_SHIFT          (0x00000007u)
#define EDMA3_CCRL_EMR_E7_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E6_MASK           (0x00000040u)
#define EDMA3_CCRL_EMR_E6_SHIFT          (0x00000006u)
#define EDMA3_CCRL_EMR_E6_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E5_MASK           (0x00000020u)
#define EDMA3_CCRL_EMR_E5_SHIFT          (0x00000005u)
#define EDMA3_CCRL_EMR_E5_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E4_MASK           (0x00000010u)
#define EDMA3_CCRL_EMR_E4_SHIFT          (0x00000004u)
#define EDMA3_CCRL_EMR_E4_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E3_MASK           (0x00000008u)
#define EDMA3_CCRL_EMR_E3_SHIFT          (0x00000003u)
#define EDMA3_CCRL_EMR_E3_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E2_MASK           (0x00000004u)
#define EDMA3_CCRL_EMR_E2_SHIFT          (0x00000002u)
#define EDMA3_CCRL_EMR_E2_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E1_MASK           (0x00000002u)
#define EDMA3_CCRL_EMR_E1_SHIFT          (0x00000001u)
#define EDMA3_CCRL_EMR_E1_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_E0_MASK           (0x00000001u)
#define EDMA3_CCRL_EMR_E0_SHIFT          (0x00000000u)
#define EDMA3_CCRL_EMR_E0_RESETVAL       (0x00000000u)

#define EDMA3_CCRL_EMR_RESETVAL          (0x00000000u)

/* EMRH */

#define EDMA3_CCRL_EMRH_E63_MASK         (0x80000000u)
#define EDMA3_CCRL_EMRH_E63_SHIFT        (0x0000001Fu)
#define EDMA3_CCRL_EMRH_E63_RESETVAL     (0x00000000u)

#define EDMA3_CCRL_EMRH_E62_MASK         (0x40000000u)
#define EDMA3_CCRL_EMRH_E62_SHIFT        (0x0000001Eu)
#define EDMA3_CCRL_EMRH_E62_RESETVAL     (0x00000000u)

#define EDMA3_CCRL_EMRH_E61_MASK         (0x20000000u)
#define EDMA3_CCRL_EMRH_E61_SHIFT        (0x0000001Du)
#define EDMA3_CCRL_EMRH_E61_RESETVAL     (0x00000000u)

#define EDMA3_CCRL_EMRH_E60_MASK         (0x10000000u)
#define EDMA3_CCRL_EMRH_E60_SHIFT        (0x0000001Cu)
#define EDMA3_CCRL_EMRH_E60_RESETVAL     (0x00000000u)

#define EDMA3_CCRL_EMRH_E59_MASK         (0x08000000u)
#define EDMA3_CCRL_EMRH_E59_SHIFT        (0x0000001Bu)
#define EDMA3_CCRL_EMRH_E59_RESETVAL     (0x00000000u)

#define EDMA3_CCRL_EMRH_E58_MASK         (0x04000000u)
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edma3_rl_cc.h - 源码说明

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