tlc5615.map.eqn

TLC5615串行DA的驱动接口,采用verilog编程

H3_cout[7] = CARRY(B1_cter[7] & (H3_cout[6]));


--H3_cs_buffer[6] is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

H3_cs_buffer[6] = B1_cter[6] $ (H3_cout[5]);

--H3L12 is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~99
--operation mode is arithmetic

H3L12 = B1_cter[6] $ (H3_cout[5]);

--H3_cout[6] is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

H3_cout[6] = CARRY(B1_cter[6] & (H3_cout[5]));


--H3_cs_buffer[5] is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

H3_cs_buffer[5] = B1_cter[5] $ (H3_cout[4]);

--H3L91 is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~100
--operation mode is arithmetic

H3L91 = B1_cter[5] $ (H3_cout[4]);

--H3_cout[5] is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

H3_cout[5] = CARRY(B1_cter[5] & (H3_cout[4]));


--H3_cs_buffer[4] is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

H3_cs_buffer[4] = B1_cter[4] $ (H3_cout[3]);

--H3L71 is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~101
--operation mode is arithmetic

H3L71 = B1_cter[4] $ (H3_cout[3]);

--H3_cout[4] is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

H3_cout[4] = CARRY(B1_cter[4] & (H3_cout[3]));


--B1_cter[0] is ctrl:HH|cter[0]
--operation mode is normal

B1_cter[0]_lut_out = B1L2 & !B1_cter[0];
B1_cter[0] = DFFEA(B1_cter[0]_lut_out, clk, !rst, , A1L7, , );

--B1L11Q is ctrl:HH|cter[0]~623
--operation mode is normal

B1L11Q = B1_cter[0];


--B1_mem_addr[5] is ctrl:HH|mem_addr[5]
--operation mode is normal

B1_mem_addr[5]_lut_out = B1L64 & B1_mem_addr[5] # !B1L64 & (F2_unreg_res_node[5] & B1L7);
B1_mem_addr[5] = DFFEA(B1_mem_addr[5]_lut_out, clk, !rst, , , , );

--B1L24Q is ctrl:HH|mem_addr[5]~305
--operation mode is normal

B1L24Q = B1_mem_addr[5];


--C1_data[8] is sin_rom:HJ|data[8]
--operation mode is normal

C1_data[8]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L22 # !B1_mem_addr[4] & (C1L32));
C1_data[8] = DFFEA(C1_data[8]_lut_out, clk, , , , , );

--C1L91Q is sin_rom:HJ|data[8]~2
--operation mode is normal

C1L91Q = C1_data[8];


--B1_wr_data[7] is ctrl:HH|wr_data[7]
--operation mode is normal

B1_wr_data[7]_lut_out = C1_data[7];
B1_wr_data[7] = DFFEA(B1_wr_data[7]_lut_out, clk, !rst, , B1L15, , );

--B1L57Q is ctrl:HH|wr_data[7]~22
--operation mode is normal

B1L57Q = B1_wr_data[7];


--D1_reg_data[6] is tlc5615_1:TLC|reg_data[6]
--operation mode is normal

D1_reg_data[6]_lut_out = D1L02 & B1_wr_data[6] # !D1L02 & (D1L87);
D1_reg_data[6] = DFFEA(D1_reg_data[6]_lut_out, clk, !rst, , , , );

--D1L86Q is tlc5615_1:TLC|reg_data[6]~1923
--operation mode is normal

D1L86Q = D1_reg_data[6];


--D1L77 is tlc5615_1:TLC|reg_data~1903
--operation mode is normal

D1L77 = D1L91 & D1_reg_data[6] # !D1L91 & (D1_reg_data[7]);

--D1L68 is tlc5615_1:TLC|reg_data~1924
--operation mode is normal

D1L68 = D1L91 & D1_reg_data[6] # !D1L91 & (D1_reg_data[7]);


--F3_unreg_res_node[8] is tlc5615_1:TLC|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[8]
--operation mode is normal

F3_unreg_res_node[8] = H9_cout[7] $ D1_cter[8];

--F3L3 is tlc5615_1:TLC|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[8]~17
--operation mode is normal

F3L3 = H9_cout[7] $ D1_cter[8];


--A1L7 is rtl~17
--operation mode is normal

A1L7 = B1L2 # !B1L54;

--A1L51 is rtl~537
--operation mode is normal

A1L51 = B1L2 # !B1L54;


--F1_unreg_res_node[8] is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[8]
--operation mode is normal

F1_unreg_res_node[8] = H3_cout[7] $ B1_cter[8];

--F1L3 is ctrl:HH|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[8]~17
--operation mode is normal

F1L3 = H3_cout[7] $ B1_cter[8];


--B1_mem_addr[2] is ctrl:HH|mem_addr[2]
--operation mode is normal

B1_mem_addr[2]_lut_out = H6_cs_buffer[2] & B1L7;
B1_mem_addr[2] = DFFEA(B1_mem_addr[2]_lut_out, clk, !rst, , B1L03, , );

--B1L63Q is ctrl:HH|mem_addr[2]~306
--operation mode is normal

B1L63Q = B1_mem_addr[2];


--B1_mem_addr[1] is ctrl:HH|mem_addr[1]
--operation mode is normal

B1_mem_addr[1]_lut_out = H6_cs_buffer[1] & B1L7;
B1_mem_addr[1] = DFFEA(B1_mem_addr[1]_lut_out, clk, !rst, , B1L03, , );

--B1L43Q is ctrl:HH|mem_addr[1]~307
--operation mode is normal

B1L43Q = B1_mem_addr[1];


--B1_mem_addr[4] is ctrl:HH|mem_addr[4]
--operation mode is normal

B1_mem_addr[4]_lut_out = B1L64 & B1_mem_addr[4] # !B1L64 & (B1L7 & H6_cs_buffer[4]);
B1_mem_addr[4] = DFFEA(B1_mem_addr[4]_lut_out, clk, !rst, , , , );

--B1L04Q is ctrl:HH|mem_addr[4]~308
--operation mode is normal

B1L04Q = B1_mem_addr[4];


--B1L3 is ctrl:HH|LessThan~108
--operation mode is normal

B1L3 = !B1_mem_addr[4] # !B1_mem_addr[5] # !B1_mem_addr[1] # !B1_mem_addr[2];

--B1L6 is ctrl:HH|LessThan~111
--operation mode is normal

B1L6 = !B1_mem_addr[4] # !B1_mem_addr[5] # !B1_mem_addr[1] # !B1_mem_addr[2];


--B1_mem_addr[3] is ctrl:HH|mem_addr[3]
--operation mode is normal

B1_mem_addr[3]_lut_out = H6_cs_buffer[3] & B1L7;
B1_mem_addr[3] = DFFEA(B1_mem_addr[3]_lut_out, clk, !rst, , B1L03, , );

--B1L83Q is ctrl:HH|mem_addr[3]~309
--operation mode is normal

B1L83Q = B1_mem_addr[3];


--B1_mem_addr[0] is ctrl:HH|mem_addr[0]
--operation mode is arithmetic

B1_mem_addr[0]_lut_out = B1L03 & !B1_mem_addr[0];
B1_mem_addr[0] = DFFEA(B1_mem_addr[0]_lut_out, clk, !rst, , B1L03, , );

--B1L13Q is ctrl:HH|mem_addr[0]~310
--operation mode is arithmetic

B1L13Q = B1_mem_addr[0];

--H6_cout[0] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

H6_cout[0] = CARRY(B1_mem_addr[0]);


--B1L7 is ctrl:HH|always3~0
--operation mode is normal

B1L7 = !B1L64 & (B1L3 # !B1_mem_addr[0] # !B1_mem_addr[3]);

--B1L8 is ctrl:HH|always3~51
--operation mode is normal

B1L8 = !B1L64 & (B1L3 # !B1_mem_addr[0] # !B1_mem_addr[3]);


--C1L22 is sin_rom:HJ|rom_4~543
--operation mode is normal

C1L22 = B1_mem_addr[3] & (B1_mem_addr[2] # B1_mem_addr[0] & B1_mem_addr[1]);

--C1L04 is sin_rom:HJ|rom_4~570
--operation mode is normal

C1L04 = B1_mem_addr[3] & (B1_mem_addr[2] # B1_mem_addr[0] & B1_mem_addr[1]);


--C1L32 is sin_rom:HJ|rom_4~544
--operation mode is normal

C1L32 = B1_mem_addr[3] # B1_mem_addr[2] & B1_mem_addr[1];

--C1L14 is sin_rom:HJ|rom_4~571
--operation mode is normal

C1L14 = B1_mem_addr[3] # B1_mem_addr[2] & B1_mem_addr[1];


--C1_data[7] is sin_rom:HJ|data[7]
--operation mode is normal

C1_data[7]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L42 # !B1_mem_addr[4] & (C1L52));
C1_data[7] = DFFEA(C1_data[7]_lut_out, clk, , , , , );

--C1L71Q is sin_rom:HJ|data[7]~3
--operation mode is normal

C1L71Q = C1_data[7];


--B1_wr_data[6] is ctrl:HH|wr_data[6]
--operation mode is normal

B1_wr_data[6]_lut_out = C1_data[6];
B1_wr_data[6] = DFFEA(B1_wr_data[6]_lut_out, clk, !rst, , B1L15, , );

--B1L37Q is ctrl:HH|wr_data[6]~23
--operation mode is normal

B1L37Q = B1_wr_data[6];


--D1_reg_data[5] is tlc5615_1:TLC|reg_data[5]
--operation mode is normal

D1_reg_data[5]_lut_out = D1L02 & B1_wr_data[5] # !D1L02 & (D1L97);
D1_reg_data[5] = DFFEA(D1_reg_data[5]_lut_out, clk, !rst, , , , );

--D1L66Q is tlc5615_1:TLC|reg_data[5]~1925
--operation mode is normal

D1L66Q = D1_reg_data[5];


--D1L87 is tlc5615_1:TLC|reg_data~1905
--operation mode is normal

D1L87 = D1L91 & D1_reg_data[5] # !D1L91 & (D1_reg_data[6]);

--D1L78 is tlc5615_1:TLC|reg_data~1926
--operation mode is normal

D1L78 = D1L91 & D1_reg_data[5] # !D1L91 & (D1_reg_data[6]);


--H6_cs_buffer[4] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

H6_cs_buffer[4] = B1_mem_addr[4] $ (H6_cout[3]);

--H6L51 is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~56
--operation mode is arithmetic

H6L51 = B1_mem_addr[4] $ (H6_cout[3]);

--H6_cout[4] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

H6_cout[4] = CARRY(B1_mem_addr[4] & (H6_cout[3]));


--F2_unreg_res_node[5] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[5]
--operation mode is normal

F2_unreg_res_node[5] = H6_cout[4] $ B1_mem_addr[5];

--F2L3 is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[5]~11
--operation mode is normal

F2L3 = H6_cout[4] $ B1_mem_addr[5];


--H6_cs_buffer[2] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

H6_cs_buffer[2] = B1_mem_addr[2] $ (H6_cout[1]);

--H6L11 is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~57
--operation mode is arithmetic

H6L11 = B1_mem_addr[2] $ (H6_cout[1]);

--H6_cout[2] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

H6_cout[2] = CARRY(B1_mem_addr[2] & (H6_cout[1]));


--H6_cs_buffer[1] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

H6_cs_buffer[1] = B1_mem_addr[1] $ (H6_cout[0]);

--H6L9 is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~58
--operation mode is arithmetic

H6L9 = B1_mem_addr[1] $ (H6_cout[0]);

--H6_cout[1] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

H6_cout[1] = CARRY(B1_mem_addr[1] & (H6_cout[0]));


--H6_cs_buffer[3] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

H6_cs_buffer[3] = B1_mem_addr[3] $ (H6_cout[2]);

--H6L31 is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~59
--operation mode is arithmetic

H6L31 = B1_mem_addr[3] $ (H6_cout[2]);

--H6_cout[3] is ctrl:HH|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

H6_cout[3] = CARRY(B1_mem_addr[3] & (H6_cout[2]));


--B1L64 is ctrl:HH|reduce_nor~2
--operation mode is normal

B1L64 = B1_cter[2] # !B1L94;

--B1L85 is ctrl:HH|reduce_nor~106
--operation mode is normal

B1L85 = B1_cter[2] # !B1L94;


--C1L42 is sin_rom:HJ|rom_4~546
--operation mode is normal

C1L42 = B1_mem_addr[3] & (B1_mem_addr[1] & (B1_mem_addr[2] # !B1_mem_addr[0]) # !B1_mem_addr[1] & (!B1_mem_addr[2]));

--C1L24 is sin_rom:HJ|rom_4~572
--operation mode is normal

C1L24 = B1_mem_addr[3] & (B1_mem_addr[1] & (B1_mem_addr[2] # !B1_mem_addr[0]) # !B1_mem_addr[1] & (!B1_mem_addr[2]));


--C1L52 is sin_rom:HJ|rom_4~547
--operation mode is normal

C1L52 = B1_mem_addr[0] & (B1_mem_addr[3] # B1_mem_addr[1] $ B1_mem_addr[2]) # !B1_mem_addr[0] & (B1_mem_addr[1] & (B1_mem_addr[3]) # !B1_mem_addr[1] & B1_mem_addr[2]);

--C1L34 is sin_rom:HJ|rom_4~573
--operation mode is normal

C1L34 = B1_mem_addr[0] & (B1_mem_addr[3] # B1_mem_addr[1] $ B1_mem_addr[2]) # !B1_mem_addr[0] & (B1_mem_addr[1] & (B1_mem_addr[3]) # !B1_mem_addr[1] & B1_mem_addr[2]);


--C1_data[6] is sin_rom:HJ|data[6]
--operation mode is normal

C1_data[6]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L62 # !B1_mem_addr[4] & (C1L72));
C1_data[6] = DFFEA(C1_data[6]_lut_out, clk, , , , , );

--C1L51Q is sin_rom:HJ|data[6]~4
--operation mode is normal

C1L51Q = C1_data[6];


--B1_wr_data[5] is ctrl:HH|wr_data[5]
--operation mode is normal

B1_wr_data[5]_lut_out = C1_data[5];
B1_wr_data[5] = DFFEA(B1_wr_data[5]_lut_out, clk, !rst, , B1L15, , );

--B1L17Q is ctrl:HH|wr_data[5]~24
--operation mode is normal

B1L17Q = B1_wr_data[5];