tlc5615.fit.eqn

TLC5615串行DA的驱动接口,采用verilog编程

--D1_reg_data[4] is tlc5615_1:TLC|reg_data[4] at LC1_E27
--operation mode is normal

D1_reg_data[4]_lut_out = D1L02 & B1_wr_data[4] # !D1L02 & (D1L08);
D1_reg_data[4] = DFFEA(D1_reg_data[4]_lut_out, GLOBAL(clk), !rst, , , , );

--D1L46Q is tlc5615_1:TLC|reg_data[4]~1927 at LC1_E27
--operation mode is normal

D1L46Q = D1_reg_data[4];


--D1L97 is tlc5615_1:TLC|reg_data~1907 at LC4_E27
--operation mode is normal

D1L97 = D1L91 & D1_reg_data[4] # !D1L91 & (D1_reg_data[5]);

--D1L88 is tlc5615_1:TLC|reg_data~1928 at LC4_E27
--operation mode is normal

D1L88 = D1L91 & D1_reg_data[4] # !D1L91 & (D1_reg_data[5]);


--C1L62 is sin_rom:HJ|rom_4~549 at LC4_E36
--operation mode is normal

C1L62 = B1_mem_addr[0] & B1_mem_addr[2] & (B1_mem_addr[1] # B1_mem_addr[3]) # !B1_mem_addr[0] & B1_mem_addr[1] & (B1_mem_addr[2] $ B1_mem_addr[3]);

--C1L44 is sin_rom:HJ|rom_4~574 at LC4_E36
--operation mode is normal

C1L44 = B1_mem_addr[0] & B1_mem_addr[2] & (B1_mem_addr[1] # B1_mem_addr[3]) # !B1_mem_addr[0] & B1_mem_addr[1] & (B1_mem_addr[2] $ B1_mem_addr[3]);


--C1L72 is sin_rom:HJ|rom_4~550 at LC5_E36
--operation mode is normal

C1L72 = B1_mem_addr[3] & (B1_mem_addr[2] # B1_mem_addr[0] $ !B1_mem_addr[1]) # !B1_mem_addr[3] & (B1_mem_addr[2] $ (!B1_mem_addr[0] & B1_mem_addr[1]));

--C1L54 is sin_rom:HJ|rom_4~575 at LC5_E36
--operation mode is normal

C1L54 = B1_mem_addr[3] & (B1_mem_addr[2] # B1_mem_addr[0] $ !B1_mem_addr[1]) # !B1_mem_addr[3] & (B1_mem_addr[2] $ (!B1_mem_addr[0] & B1_mem_addr[1]));


--C1_data[5] is sin_rom:HJ|data[5] at LC3_E40
--operation mode is normal

C1_data[5]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L82 # !B1_mem_addr[4] & (C1L92));
C1_data[5] = DFFEA(C1_data[5]_lut_out, GLOBAL(clk), , , , , );

--C1L31Q is sin_rom:HJ|data[5]~5 at LC3_E40
--operation mode is normal

C1L31Q = C1_data[5];


--B1_wr_data[4] is ctrl:HH|wr_data[4] at LC5_E27
--operation mode is normal

B1_wr_data[4]_lut_out = C1_data[4];
B1_wr_data[4] = DFFEA(B1_wr_data[4]_lut_out, GLOBAL(clk), !rst, , B1L15, , );

--B1L96Q is ctrl:HH|wr_data[4]~25 at LC5_E27
--operation mode is normal

B1L96Q = B1_wr_data[4];


--D1_reg_data[3] is tlc5615_1:TLC|reg_data[3] at LC2_E29
--operation mode is normal

D1_reg_data[3]_lut_out = D1L02 & B1_wr_data[3] # !D1L02 & (D1L18);
D1_reg_data[3] = DFFEA(D1_reg_data[3]_lut_out, GLOBAL(clk), !rst, , , , );

--D1L26Q is tlc5615_1:TLC|reg_data[3]~1929 at LC2_E29
--operation mode is normal

D1L26Q = D1_reg_data[3];


--D1L08 is tlc5615_1:TLC|reg_data~1909 at LC1_E29
--operation mode is normal

D1L08 = D1L91 & D1_reg_data[3] # !D1L91 & (D1_reg_data[4]);

--D1L98 is tlc5615_1:TLC|reg_data~1930 at LC1_E29
--operation mode is normal

D1L98 = D1L91 & D1_reg_data[3] # !D1L91 & (D1_reg_data[4]);


--C1L82 is sin_rom:HJ|rom_4~552 at LC4_E40
--operation mode is normal

C1L82 = B1_mem_addr[2] & (B1_mem_addr[0] & !B1_mem_addr[3] # !B1_mem_addr[1]) # !B1_mem_addr[2] & B1_mem_addr[3] & (B1_mem_addr[0] $ B1_mem_addr[1]);

--C1L64 is sin_rom:HJ|rom_4~576 at LC4_E40
--operation mode is normal

C1L64 = B1_mem_addr[2] & (B1_mem_addr[0] & !B1_mem_addr[3] # !B1_mem_addr[1]) # !B1_mem_addr[2] & B1_mem_addr[3] & (B1_mem_addr[0] $ B1_mem_addr[1]);


--C1L92 is sin_rom:HJ|rom_4~553 at LC5_E40
--operation mode is normal

C1L92 = B1_mem_addr[1] & (B1_mem_addr[2] & (B1_mem_addr[3]) # !B1_mem_addr[2] & !B1_mem_addr[0]) # !B1_mem_addr[1] & (B1_mem_addr[0] $ (!B1_mem_addr[2] & B1_mem_addr[3]));

--C1L74 is sin_rom:HJ|rom_4~577 at LC5_E40
--operation mode is normal

C1L74 = B1_mem_addr[1] & (B1_mem_addr[2] & (B1_mem_addr[3]) # !B1_mem_addr[2] & !B1_mem_addr[0]) # !B1_mem_addr[1] & (B1_mem_addr[0] $ (!B1_mem_addr[2] & B1_mem_addr[3]));


--C1_data[4] is sin_rom:HJ|data[4] at LC6_E27
--operation mode is normal

C1_data[4]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L03 # !B1_mem_addr[4] & (C1L13));
C1_data[4] = DFFEA(C1_data[4]_lut_out, GLOBAL(clk), , , , , );

--C1L11Q is sin_rom:HJ|data[4]~6 at LC6_E27
--operation mode is normal

C1L11Q = C1_data[4];


--B1_wr_data[3] is ctrl:HH|wr_data[3] at LC2_E34
--operation mode is normal

B1_wr_data[3]_lut_out = C1_data[3];
B1_wr_data[3] = DFFEA(B1_wr_data[3]_lut_out, GLOBAL(clk), !rst, , B1L15, , );

--B1L76Q is ctrl:HH|wr_data[3]~26 at LC2_E34
--operation mode is normal

B1L76Q = B1_wr_data[3];


--D1_reg_data[2] is tlc5615_1:TLC|reg_data[2] at LC3_E29
--operation mode is normal

D1_reg_data[2]_lut_out = D1L02 & B1_wr_data[2] # !D1L02 & (D1L28);
D1_reg_data[2] = DFFEA(D1_reg_data[2]_lut_out, GLOBAL(clk), !rst, , , , );

--D1L06Q is tlc5615_1:TLC|reg_data[2]~1931 at LC3_E29
--operation mode is normal

D1L06Q = D1_reg_data[2];


--D1L18 is tlc5615_1:TLC|reg_data~1911 at LC4_E29
--operation mode is normal

D1L18 = D1L91 & D1_reg_data[2] # !D1L91 & (D1_reg_data[3]);

--D1L09 is tlc5615_1:TLC|reg_data~1932 at LC4_E29
--operation mode is normal

D1L09 = D1L91 & D1_reg_data[2] # !D1L91 & (D1_reg_data[3]);


--C1L03 is sin_rom:HJ|rom_4~555 at LC7_E27
--operation mode is normal

C1L03 = B1_mem_addr[0] & (B1_mem_addr[3] $ (B1_mem_addr[1] # B1_mem_addr[2])) # !B1_mem_addr[0] & (B1_mem_addr[1] & B1_mem_addr[2] # !B1_mem_addr[1] & (B1_mem_addr[3]));

--C1L84 is sin_rom:HJ|rom_4~578 at LC7_E27
--operation mode is normal

C1L84 = B1_mem_addr[0] & (B1_mem_addr[3] $ (B1_mem_addr[1] # B1_mem_addr[2])) # !B1_mem_addr[0] & (B1_mem_addr[1] & B1_mem_addr[2] # !B1_mem_addr[1] & (B1_mem_addr[3]));


--C1L13 is sin_rom:HJ|rom_4~556 at LC8_E27
--operation mode is normal

C1L13 = B1_mem_addr[0] & (B1_mem_addr[3] $ (!B1_mem_addr[2] # !B1_mem_addr[1])) # !B1_mem_addr[0] & B1_mem_addr[2] & (B1_mem_addr[1] # B1_mem_addr[3]);

--C1L94 is sin_rom:HJ|rom_4~579 at LC8_E27
--operation mode is normal

C1L94 = B1_mem_addr[0] & (B1_mem_addr[3] $ (!B1_mem_addr[2] # !B1_mem_addr[1])) # !B1_mem_addr[0] & B1_mem_addr[2] & (B1_mem_addr[1] # B1_mem_addr[3]);


--C1_data[3] is sin_rom:HJ|data[3] at LC4_E34
--operation mode is normal

C1_data[3]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L23 # !B1_mem_addr[4] & (C1L33));
C1_data[3] = DFFEA(C1_data[3]_lut_out, GLOBAL(clk), , , , , );

--C1L9Q is sin_rom:HJ|data[3]~7 at LC4_E34
--operation mode is normal

C1L9Q = C1_data[3];


--B1_wr_data[2] is ctrl:HH|wr_data[2] at LC1_E37
--operation mode is normal

B1_wr_data[2]_lut_out = C1_data[2];
B1_wr_data[2] = DFFEA(B1_wr_data[2]_lut_out, GLOBAL(clk), !rst, , B1L15, , );

--B1L56Q is ctrl:HH|wr_data[2]~27 at LC1_E37
--operation mode is normal

B1L56Q = B1_wr_data[2];


--D1_reg_data[1] is tlc5615_1:TLC|reg_data[1] at LC5_E29
--operation mode is normal

D1_reg_data[1]_lut_out = D1L02 & B1_wr_data[1] # !D1L02 & (D1L38);
D1_reg_data[1] = DFFEA(D1_reg_data[1]_lut_out, GLOBAL(clk), !rst, , , , );

--D1L85Q is tlc5615_1:TLC|reg_data[1]~1933 at LC5_E29
--operation mode is normal

D1L85Q = D1_reg_data[1];


--D1L28 is tlc5615_1:TLC|reg_data~1913 at LC6_E29
--operation mode is normal

D1L28 = D1L91 & D1_reg_data[1] # !D1L91 & (D1_reg_data[2]);

--D1L19 is tlc5615_1:TLC|reg_data~1934 at LC6_E29
--operation mode is normal

D1L19 = D1L91 & D1_reg_data[1] # !D1L91 & (D1_reg_data[2]);


--C1L23 is sin_rom:HJ|rom_4~558 at LC1_E40
--operation mode is normal

C1L23 = B1_mem_addr[0] & (B1_mem_addr[3] # !B1_mem_addr[1] & B1_mem_addr[2]) # !B1_mem_addr[0] & (B1_mem_addr[2] & (B1_mem_addr[3]) # !B1_mem_addr[2] & B1_mem_addr[1] & !B1_mem_addr[3]);

--C1L05 is sin_rom:HJ|rom_4~580 at LC1_E40
--operation mode is normal

C1L05 = B1_mem_addr[0] & (B1_mem_addr[3] # !B1_mem_addr[1] & B1_mem_addr[2]) # !B1_mem_addr[0] & (B1_mem_addr[2] & (B1_mem_addr[3]) # !B1_mem_addr[2] & B1_mem_addr[1] & !B1_mem_addr[3]);


--C1L33 is sin_rom:HJ|rom_4~559 at LC5_E34
--operation mode is normal

C1L33 = B1_mem_addr[0] & B1_mem_addr[3] & (B1_mem_addr[2] # !B1_mem_addr[1]) # !B1_mem_addr[0] & (B1_mem_addr[3] $ (B1_mem_addr[1] & B1_mem_addr[2]));

--C1L15 is sin_rom:HJ|rom_4~581 at LC5_E34
--operation mode is normal

C1L15 = B1_mem_addr[0] & B1_mem_addr[3] & (B1_mem_addr[2] # !B1_mem_addr[1]) # !B1_mem_addr[0] & (B1_mem_addr[3] $ (B1_mem_addr[1] & B1_mem_addr[2]));


--C1_data[2] is sin_rom:HJ|data[2] at LC6_E37
--operation mode is normal

C1_data[2]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L43 # !B1_mem_addr[4] & (C1L53));
C1_data[2] = DFFEA(C1_data[2]_lut_out, GLOBAL(clk), , , , , );

--C1L7Q is sin_rom:HJ|data[2]~8 at LC6_E37
--operation mode is normal

C1L7Q = C1_data[2];


--B1_wr_data[1] is ctrl:HH|wr_data[1] at LC1_E36
--operation mode is normal

B1_wr_data[1]_lut_out = C1_data[1];
B1_wr_data[1] = DFFEA(B1_wr_data[1]_lut_out, GLOBAL(clk), !rst, , B1L15, , );

--B1L36Q is ctrl:HH|wr_data[1]~28 at LC1_E36
--operation mode is normal

B1L36Q = B1_wr_data[1];


--D1_reg_data[0] is tlc5615_1:TLC|reg_data[0] at LC7_E29
--operation mode is normal

D1_reg_data[0]_lut_out = D1L02 & B1_wr_data[0] # !D1L02 & (D1L91 # D1_reg_data[0]);
D1_reg_data[0] = DFFEA(D1_reg_data[0]_lut_out, GLOBAL(clk), !rst, , , , );

--D1L65Q is tlc5615_1:TLC|reg_data[0]~1935 at LC7_E29
--operation mode is normal

D1L65Q = D1_reg_data[0];


--D1L38 is tlc5615_1:TLC|reg_data~1915 at LC8_E29
--operation mode is normal

D1L38 = D1L91 & D1_reg_data[0] # !D1L91 & (D1_reg_data[1]);

--D1L29 is tlc5615_1:TLC|reg_data~1936 at LC8_E29
--operation mode is normal

D1L29 = D1L91 & D1_reg_data[0] # !D1L91 & (D1_reg_data[1]);


--C1L43 is sin_rom:HJ|rom_4~561 at LC7_E37
--operation mode is normal

C1L43 = B1_mem_addr[1] & (B1_mem_addr[0] # B1_mem_addr[2]) # !B1_mem_addr[1] & (B1_mem_addr[3] & !B1_mem_addr[0] # !B1_mem_addr[3] & (B1_mem_addr[2]));

--C1L25 is sin_rom:HJ|rom_4~582 at LC7_E37
--operation mode is normal

C1L25 = B1_mem_addr[1] & (B1_mem_addr[0] # B1_mem_addr[2]) # !B1_mem_addr[1] & (B1_mem_addr[3] & !B1_mem_addr[0] # !B1_mem_addr[3] & (B1_mem_addr[2]));


--C1L53 is sin_rom:HJ|rom_4~562 at LC8_E37
--operation mode is normal

C1L53 = B1_mem_addr[1] & (B1_mem_addr[2] # B1_mem_addr[0] & !B1_mem_addr[3]);

--C1L35 is sin_rom:HJ|rom_4~583 at LC8_E37
--operation mode is normal

C1L35 = B1_mem_addr[1] & (B1_mem_addr[2] # B1_mem_addr[0] & !B1_mem_addr[3]);


--C1_data[1] is sin_rom:HJ|data[1] at LC6_E36
--operation mode is normal

C1_data[1]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L63 # !B1_mem_addr[4] & (C1L73));
C1_data[1] = DFFEA(C1_data[1]_lut_out, GLOBAL(clk), , , , , );

--C1L5Q is sin_rom:HJ|data[1]~9 at LC6_E36
--operation mode is normal

C1L5Q = C1_data[1];


--B1_wr_data[0] is ctrl:HH|wr_data[0] at LC2_E40
--operation mode is normal

B1_wr_data[0]_lut_out = C1_data[0];
B1_wr_data[0] = DFFEA(B1_wr_data[0]_lut_out, GLOBAL(clk), !rst, , B1L15, , );

--B1L16Q is ctrl:HH|wr_data[0]~29 at LC2_E40
--operation mode is normal

B1L16Q = B1_wr_data[0];


--C1L63 is sin_rom:HJ|rom_4~564 at LC7_E36
--operation mode is normal

C1L63 = B1_mem_addr[3] & (B1_mem_addr[1] & (!B1_mem_addr[2]) # !B1_mem_addr[1] & B1_mem_addr[0]) # !B1_mem_addr[3] & (B1_mem_addr[0] $ (B1_mem_addr[2]));

--C1L45 is sin_rom:HJ|rom_4~584 at LC7_E36
--operation mode is normal

C1L45 = B1_mem_addr[3] & (B1_mem_addr[1] & (!B1_mem_addr[2]) # !B1_mem_addr[1] & B1_mem_addr[0]) # !B1_mem_addr[3] & (B1_mem_addr[0] $ (B1_mem_addr[2]));


--C1L73 is sin_rom:HJ|rom_4~565 at LC8_E36
--operation mode is normal

C1L73 = B1_mem_addr[0] & !B1_mem_addr[2] & (B1_mem_addr[3] # !B1_mem_addr[1]) # !B1_mem_addr[0] & (B1_mem_addr[1] $ B1_mem_addr[2] $ B1_mem_addr[3]);

--C1L55 is sin_rom:HJ|rom_4~585 at LC8_E36
--operation mode is normal

C1L55 = B1_mem_addr[0] & !B1_mem_addr[2] & (B1_mem_addr[3] # !B1_mem_addr[1]) # !B1_mem_addr[0] & (B1_mem_addr[1] $ B1_mem_addr[2] $ B1_mem_addr[3]);


--C1_data[0] is sin_rom:HJ|data[0] at LC6_E40
--operation mode is normal

C1_data[0]_lut_out = B1_mem_addr[5] $ (B1_mem_addr[4] & !C1L83 # !B1_mem_addr[4] & (C1L93));
C1_data[0] = DFFEA(C1_data[0]_lut_out, GLOBAL(clk), , , , , );

--C1L3Q is sin_rom:HJ|data[0]~10 at LC6_E40
--operation mode is normal

C1L3Q = C1_data[0];


--C1L83 is sin_rom:HJ|rom_4~567 at LC7_E40
--operation mode is normal

C1L83 = B1_mem_addr[2] & B1_mem_addr[0] & (B1_mem_addr[3]) # !B1_mem_addr[2] & (B1_mem_addr[1] & !B1_mem_addr[0] # !B1_mem_addr[1] & (B1_mem_addr[3]));

--C1L65 is sin_rom:HJ|rom_4~586 at LC7_E40
--operation mode is normal

C1L65 = B1_mem_addr[2] & B1_mem_addr[0] & (B1_mem_addr[3]) # !B1_mem_addr[2] & (B1_mem_addr[1] & !B1_mem_addr[0] # !B1_mem_addr[1] & (B1_mem_addr[3]));


--C1L93 is sin_rom:HJ|rom_4~568 at LC8_E40
--operation mode is normal

C1L93 = B1_mem_addr[0] & (B1_mem_addr[3] # !B1_mem_addr[1] & B1_mem_addr[2]) # !B1_mem_addr[0] & (B1_mem_addr[1] $ B1_mem_addr[2]);

--C1L75 is sin_rom:HJ|rom_4~587 at LC8_E40
--operation mode is normal

C1L75 = B1_mem_addr[0] & (B1_mem_addr[3] # !B1_mem_addr[1] & B1_mem_addr[2]) # !B1_mem_addr[0] & (B1_mem_addr[1] $ B1_mem_addr[2]);


--B1L03 is ctrl:HH|mem_addr[0]~301 at LC1_E47
--operation mode is normal

B1L03 = !B1L64;

--B1L23 is ctrl:HH|mem_addr[0]~311 at LC1_E47
--operation mode is normal

B1L23 = !B1L64;


--clk is clk at PIN_79
--operation mode is input

clk = INPUT();


--rst is rst at PIN_180
--operation mode is input

rst = INPUT();


--SIN is SIN at PIN_53
--operation mode is output

SIN = OUTPUT(!D1_SIN);


--SCL is SCL at PIN_55
--operation mode is output

SCL = OUTPUT(!D1_SCL);


--SNCS is SNCS at PIN_57
--operation mode is output

SNCS = OUTPUT(!D1_SNCS);