tlc5615.map.rpt

TLC5615串行DA的驱动接口,采用verilog编程

;             |a_csnbuffer:result_node| ; 7 (7)       ; 0            ; 0           ; 0    ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 7 (7)           ; |tlc5615|tlc5615_1:TLC|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 66    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 56    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 33    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; tlc5615_1:TLC|SIN                      ; 2       ;
; tlc5615_1:TLC|SCL                      ; 7       ;
; tlc5615_1:TLC|SNCS                     ; 12      ;
; tlc5615_1:TLC|ncs_d                    ; 2       ;
; ctrl:HH|ncs                            ; 4       ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: tlc5615_1:TLC|lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+-----------------------------------------------+
; Parameter Name         ; Value       ; Type                                          ;
+------------------------+-------------+-----------------------------------------------+
; LPM_WIDTH              ; 9           ; Untyped                                       ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                       ;
; LPM_DIRECTION          ; ADD         ; Untyped                                       ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                       ;
; LPM_PIPELINE           ; 0           ; Untyped                                       ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                       ;
; REGISTERED_AT_END      ; 0           ; Untyped                                       ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                       ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                       ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                       ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                            ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                       ;
; USE_WYS                ; OFF         ; Untyped                                       ;
; STYLE                  ; FAST        ; Untyped                                       ;
; CBXI_PARAMETER         ; add_sub_plh ; Untyped                                       ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                    ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                  ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                  ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                ;
+------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: ctrl:HH|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+-----------------------------------------+
; Parameter Name         ; Value       ; Type                                    ;
+------------------------+-------------+-----------------------------------------+
; LPM_WIDTH              ; 9           ; Untyped                                 ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                 ;
; LPM_DIRECTION          ; ADD         ; Untyped                                 ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                 ;
; LPM_PIPELINE           ; 0           ; Untyped                                 ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                 ;
; REGISTERED_AT_END      ; 0           ; Untyped                                 ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                 ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                      ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                 ;
; USE_WYS                ; OFF         ; Untyped                                 ;
; STYLE                  ; FAST        ; Untyped                                 ;
; CBXI_PARAMETER         ; add_sub_plh ; Untyped                                 ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                          ;
+------------------------+-------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: ctrl:HH|lpm_add_sub:add_rtl_2 ;
+------------------------+-------------+-----------------------------------------+
; Parameter Name         ; Value       ; Type                                    ;
+------------------------+-------------+-----------------------------------------+
; LPM_WIDTH              ; 6           ; Untyped                                 ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                 ;
; LPM_DIRECTION          ; ADD         ; Untyped                                 ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                                 ;
; LPM_PIPELINE           ; 0           ; Untyped                                 ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                 ;
; REGISTERED_AT_END      ; 0           ; Untyped                                 ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                 ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                      ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                 ;
; USE_WYS                ; OFF         ; Untyped                                 ;
; STYLE                  ; FAST        ; Untyped                                 ;
; CBXI_PARAMETER         ; add_sub_mlh ; Untyped                                 ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                          ;
+------------------------+-------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/work/FPGA资料/DAC/lzh2/tlc5615.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Sep 23 17:29:35 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off tlc5615 -c tlc5615
Warning: (10268) Verilog HDL information at tlc5615.v(159): Always Construct contains both blocking and non-blocking assignments
Info: Using design file tlc5615.v, which is not specified as a design file for the current project, but contains definitions for 4 design units and 4 entities in project
    Info: Found entity 1: tlc5615
    Info: Found entity 2: ctrl
    Info: Found entity 3: tlc5615_1
    Info: Found entity 4: sin_rom
Info: Elaborating entity "tlc5615" for the top level hierarchy
Info: Elaborating entity "ctrl" for hierarchy "ctrl:HH"
Info: Elaborating entity "sin_rom" for hierarchy "sin_rom:HJ"
Info: Elaborating entity "tlc5615_1" for hierarchy "tlc5615_1:TLC"
Info: (10035) Verilog HDL or VHDL information at tlc5615.v(114): object "sncs_d" declared but not used
Warning: Verilog HDL assignment warning at tlc5615.v(131): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at tlc5615.v(196): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at tlc5615.v(206): truncated value with size 32 to match size of target (2)
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Registers with preset signals will power-up high
Info: Implemented 147 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 3 output pins
    Info: Implemented 142 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Sat Sep 23 17:29:37 2006
    Info: Elapsed time: 00:00:02