tlc5615.tan.qmsg

TLC5615串行DA的驱动接口,采用verilog编程

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ctrl:HH\|cter\[7\] register ctrl:HH\|mem_addr\[0\] 73.53 MHz 13.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 73.53 MHz between source register \"ctrl:HH\|cter\[7\]\" and destination register \"ctrl:HH\|mem_addr\[0\]\" (period= 13.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.800 ns + Longest register register " "Info: + Longest register to register delay is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ctrl:HH\|cter\[7\] 1 REG LC7_E45 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_E45; Fanout = 3; REG Node = 'ctrl:HH\|cter\[7\]'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "" { ctrl:HH|cter[7] } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 51 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 2.400 ns ctrl:HH\|reduce_nor~94 2 COMB LC1_E45 3 " "Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC1_E45; Fanout = 3; COMB Node = 'ctrl:HH\|reduce_nor~94'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "2.400 ns" { ctrl:HH|cter[7] ctrl:HH|reduce_nor~94 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 5.500 ns ctrl:HH\|reduce_nor~96 3 COMB LC3_E47 2 " "Info: 3: + IC(1.100 ns) + CELL(2.000 ns) = 5.500 ns; Loc. = LC3_E47; Fanout = 2; COMB Node = 'ctrl:HH\|reduce_nor~96'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "3.100 ns" { ctrl:HH|reduce_nor~94 ctrl:HH|reduce_nor~96 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 7.400 ns ctrl:HH\|reduce_nor~2 4 COMB LC2_E47 4 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.400 ns; Loc. = LC2_E47; Fanout = 4; COMB Node = 'ctrl:HH\|reduce_nor~2'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { ctrl:HH|reduce_nor~96 ctrl:HH|reduce_nor~2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 9.300 ns ctrl:HH\|mem_addr\[0\]~301 5 COMB LC1_E47 5 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.300 ns; Loc. = LC1_E47; Fanout = 5; COMB Node = 'ctrl:HH\|mem_addr\[0\]~301'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { ctrl:HH|reduce_nor~2 ctrl:HH|mem_addr[0]~301 } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.500 ns) 11.800 ns ctrl:HH\|mem_addr\[0\] 6 REG LC3_E49 20 " "Info: 6: + IC(1.000 ns) + CELL(1.500 ns) = 11.800 ns; Loc. = LC3_E49; Fanout = 20; REG Node = 'ctrl:HH\|mem_addr\[0\]'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "2.500 ns" { ctrl:HH|mem_addr[0]~301 ctrl:HH|mem_addr[0] } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 45 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.100 ns 77.12 % " "Info: Total cell delay = 9.100 ns ( 77.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 22.88 % " "Info: Total interconnect delay = 2.700 ns ( 22.88 % )" {  } {  } 0}  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "11.800 ns" { ctrl:HH|cter[7] ctrl:HH|reduce_nor~94 ctrl:HH|reduce_nor~96 ctrl:HH|reduce_nor~2 ctrl:HH|mem_addr[0]~301 ctrl:HH|mem_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.800 ns" { ctrl:HH|cter[7] ctrl:HH|reduce_nor~94 ctrl:HH|reduce_nor~96 ctrl:HH|reduce_nor~2 ctrl:HH|mem_addr[0]~301 ctrl:HH|mem_addr[0] } { 0.000ns 0.200ns 1.100ns 0.200ns 0.200ns 1.000ns } { 0.000ns 2.200ns 2.000ns 1.700ns 1.700ns 1.500ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 66 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 66; CLK Node = 'clk'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns ctrl:HH\|mem_addr\[0\] 2 REG LC3_E49 20 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_E49; Fanout = 20; REG Node = 'ctrl:HH\|mem_addr\[0\]'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.400 ns" { clk ctrl:HH|mem_addr[0] } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 45 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { clk ctrl:HH|mem_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out ctrl:HH|mem_addr[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 66 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 66; CLK Node = 'clk'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns ctrl:HH\|cter\[7\] 2 REG LC7_E45 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_E45; Fanout = 3; REG Node = 'ctrl:HH\|cter\[7\]'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.400 ns" { clk ctrl:HH|cter[7] } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 51 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { clk ctrl:HH|cter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out ctrl:HH|cter[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { clk ctrl:HH|mem_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out ctrl:HH|mem_addr[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { clk ctrl:HH|cter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out ctrl:HH|cter[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 51 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 45 -1 0 } }  } 0}  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "11.800 ns" { ctrl:HH|cter[7] ctrl:HH|reduce_nor~94 ctrl:HH|reduce_nor~96 ctrl:HH|reduce_nor~2 ctrl:HH|mem_addr[0]~301 ctrl:HH|mem_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.800 ns" { ctrl:HH|cter[7] ctrl:HH|reduce_nor~94 ctrl:HH|reduce_nor~96 ctrl:HH|reduce_nor~2 ctrl:HH|mem_addr[0]~301 ctrl:HH|mem_addr[0] } { 0.000ns 0.200ns 1.100ns 0.200ns 0.200ns 1.000ns } { 0.000ns 2.200ns 2.000ns 1.700ns 1.700ns 1.500ns } } } { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { clk ctrl:HH|mem_addr[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out ctrl:HH|mem_addr[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { clk ctrl:HH|cter[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out ctrl:HH|cter[7] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk SNCS tlc5615_1:TLC\|SNCS 13.200 ns register " "Info: tco from clock \"clk\" to destination pin \"SNCS\" through register \"tlc5615_1:TLC\|SNCS\" is 13.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 66 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 66; CLK Node = 'clk'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "" { clk } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns tlc5615_1:TLC\|SNCS 2 REG LC6_E44 12 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_E44; Fanout = 12; REG Node = 'tlc5615_1:TLC\|SNCS'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.400 ns" { clk tlc5615_1:TLC|SNCS } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 103 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0}  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { clk tlc5615_1:TLC|SNCS } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out tlc5615_1:TLC|SNCS } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 103 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.200 ns + Longest register pin " "Info: + Longest register to pin delay is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tlc5615_1:TLC\|SNCS 1 REG LC6_E44 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_E44; Fanout = 12; REG Node = 'tlc5615_1:TLC\|SNCS'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "" { tlc5615_1:TLC|SNCS } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 103 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(8.500 ns) 10.200 ns SNCS 2 PIN PIN_57 0 " "Info: 2: + IC(1.700 ns) + CELL(8.500 ns) = 10.200 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'SNCS'" {  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "10.200 ns" { tlc5615_1:TLC|SNCS SNCS } "NODE_NAME" } "" } } { "tlc5615.v" "" { Text "D:/work/FPGA资料/DAC/lzh2/tlc5615.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns 83.33 % " "Info: Total cell delay = 8.500 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 16.67 % " "Info: Total interconnect delay = 1.700 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "10.200 ns" { tlc5615_1:TLC|SNCS SNCS } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.200 ns" { tlc5615_1:TLC|SNCS SNCS } { 0.000ns 1.700ns } { 0.000ns 8.500ns } } }  } 0}  } { { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "1.900 ns" { clk tlc5615_1:TLC|SNCS } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clk clk~out tlc5615_1:TLC|SNCS } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" "" { Report "D:/work/FPGA资料/DAC/lzh2/db/tlc5615_cmp.qrpt" Compiler "tlc5615" "UNKNOWN" "V1" "D:/work/FPGA资料/DAC/lzh2/db/tlc5615.quartus_db" { Floorplan "D:/work/FPGA资料/DAC/lzh2/" "" "10.200 ns" { tlc5615_1:TLC|SNCS SNCS } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.200 ns" { tlc5615_1:TLC|SNCS SNCS } { 0.000ns 1.700ns } { 0.000ns 8.500ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 23 17:29:54 2006 " "Info: Processing ended: Sat Sep 23 17:29:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}