tlc5615.tan.rpt

TLC5615串行DA的驱动接口,采用verilog编程

; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; ctrl:HH|cter[8]           ; ctrl:HH|cter[1]           ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; tlc5615_1:TLC|cter[2]     ; tlc5615_1:TLC|cter[1]     ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; tlc5615_1:TLC|cter[2]     ; tlc5615_1:TLC|cter[2]     ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; tlc5615_1:TLC|cter[2]     ; tlc5615_1:TLC|cter[3]     ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; tlc5615_1:TLC|cter[6]     ; tlc5615_1:TLC|cter[5]     ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; ctrl:HH|cter[2]           ; ctrl:HH|wr_data[8]        ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; N/A                                     ; 112.36 MHz ( period = 8.900 ns )                    ; ctrl:HH|cter[8]           ; ctrl:HH|cter[2]           ; clk        ; clk      ; None                        ; None                      ; 7.100 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                           ;                           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+--------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To   ; From Clock ;
+-------+--------------+------------+--------------------+------+------------+
; N/A   ; None         ; 13.200 ns  ; tlc5615_1:TLC|SNCS ; SNCS ; clk        ;
; N/A   ; None         ; 13.200 ns  ; tlc5615_1:TLC|SCL  ; SCL  ; clk        ;
; N/A   ; None         ; 13.000 ns  ; tlc5615_1:TLC|SIN  ; SIN  ; clk        ;
+-------+--------------+------------+--------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Sep 23 17:29:53 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tlc5615 -c tlc5615
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 73.53 MHz between source register "ctrl:HH|cter[7]" and destination register "ctrl:HH|mem_addr[0]" (period= 13.6 ns)
    Info: + Longest register to register delay is 11.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_E45; Fanout = 3; REG Node = 'ctrl:HH|cter[7]'
        Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC1_E45; Fanout = 3; COMB Node = 'ctrl:HH|reduce_nor~94'
        Info: 3: + IC(1.100 ns) + CELL(2.000 ns) = 5.500 ns; Loc. = LC3_E47; Fanout = 2; COMB Node = 'ctrl:HH|reduce_nor~96'
        Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 7.400 ns; Loc. = LC2_E47; Fanout = 4; COMB Node = 'ctrl:HH|reduce_nor~2'
        Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 9.300 ns; Loc. = LC1_E47; Fanout = 5; COMB Node = 'ctrl:HH|mem_addr[0]~301'
        Info: 6: + IC(1.000 ns) + CELL(1.500 ns) = 11.800 ns; Loc. = LC3_E49; Fanout = 20; REG Node = 'ctrl:HH|mem_addr[0]'
        Info: Total cell delay = 9.100 ns ( 77.12 % )
        Info: Total interconnect delay = 2.700 ns ( 22.88 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 66; CLK Node = 'clk'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_E49; Fanout = 20; REG Node = 'ctrl:HH|mem_addr[0]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: - Longest clock path from clock "clk" to source register is 1.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 66; CLK Node = 'clk'
            Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_E45; Fanout = 3; REG Node = 'ctrl:HH|cter[7]'
            Info: Total cell delay = 0.500 ns ( 26.32 % )
            Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tco from clock "clk" to destination pin "SNCS" through register "tlc5615_1:TLC|SNCS" is 13.200 ns
    Info: + Longest clock path from clock "clk" to source register is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 66; CLK Node = 'clk'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_E44; Fanout = 12; REG Node = 'tlc5615_1:TLC|SNCS'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 10.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_E44; Fanout = 12; REG Node = 'tlc5615_1:TLC|SNCS'
        Info: 2: + IC(1.700 ns) + CELL(8.500 ns) = 10.200 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'SNCS'
        Info: Total cell delay = 8.500 ns ( 83.33 % )
        Info: Total interconnect delay = 1.700 ns ( 16.67 % )
Info: Quartus II Timing Analyzer was suc