tlc5615.v

TLC5615串行DA的驱动接口,采用verilog编程

module tlc5615(clk,rst,SIN,SCL,SNCS);
input clk;
input rst;
output SIN,SCL,SNCS;
//reg [8:0]cter;
wire ncs; //内部用的数据时钟?
wire ack; //响应信号
wire [9:0] wr_data,mem_data;
wire [7:0] mem_addr;
//reg SIN,SCL,SNCS;
//SCL serial clk output to TLC5615 ; SNCS chip select for TLC5615;
//SIN serial data output to TLC5615;
/*
always @(posedge clk or posedge rst)
        if(rst)cter<=9'h000;
        //else if(cter<9'h01) cter<=cter+9'h001;
        //else if(cter==9'h01) cter<=9'h000;
        //cter 作为累加分频寄存器将clk分频 累加 9'h000 -> 9'h2f9: 761
        else if(cter<9'h2f9) cter<=cter+9'h001;
        else if(cter==9'h2f9) cter<=9'h000;
        else cter<=cter;

always @(posedge clk or posedge rst)
        if(rst) ncs<=1'b1;
        else if(cter==9'h2f7)ncs<=1'b0;
        else if(cter==9'h2f9)ncs<=1'b1;
        else ncs<=ncs;
*/
ctrl HH(clk,rst,ack,wr_data,ncs,mem_addr,mem_data);
sin_rom HJ(clk,mem_addr,mem_data);

tlc5615_1 TLC(clk,rst,wr_data,ncs,ack,SIN,SCL,SNCS);



endmodule

module ctrl(clk,rst,ack,wr_data,ncs,mem_addr,mem_data);
input clk;
input rst;
input ack;
input  [9:0]mem_data;
output [9:0]wr_data;
output ncs;
output [5:0]mem_addr;
reg [9:0]wr_data;
reg ncs;
reg [5:0]mem_addr;
reg ack_d;
//reg [2:0] cscter;
reg[8:0]cter;


always @(posedge clk or posedge rst)
        if(rst) ack_d<=1'b0;
        else ack_d<=ack;
        
wire ack_f=~ack & ack_d; //下降沿;

//the signal ack seem unused

always @(posedge clk or posedge rst)
        if(rst)cter<=9'h000;
        //else if(cter<9'h01) cter<=cter+9'h001;
        //else if(cter==9'h01) cter<=9'h000;
        else if(cter<9'h1f9) cter<=cter+9'h001;
        else if(cter==9'h1f9) cter<=9'h000;
        else cter<=cter;

always @(posedge clk or posedge rst)
        if(rst) ncs<=1'b1;
        else if(cter==9'h1f7)ncs<=1'b0;  //about 20us
        else if(cter==9'h1f9)ncs<=1'b1;
        else ncs<=ncs;
/*
always @(posedge clk or posedge rst)
        if(rst) cscter<=3'h0;
        else if(!ncs) cscter<=cscter+1'b1;
        else if(!ncs && cscter==3'h7)cscter<=0;
        //else if(acter==2'h3)acter<=acter;
        else cscter<=cscter;
*/
always @(posedge clk or posedge rst)
        if(rst) mem_addr<=6'h00;
        else if( cter==9'h1f3 && mem_addr<6'h3f)mem_addr<=mem_addr+6'h01;
        else if( cter==9'h1f3 && mem_addr==6'h3f)mem_addr<=6'h00;
        else mem_addr<=mem_addr;
     
always @(posedge clk or posedge rst)
        if(rst) wr_data<=10'h000;
        else if( cter==9'h0f5 )wr_data<=mem_data;
        else wr_data<=wr_data;


endmodule    

module tlc5615_1(clk,rst,wr_data,
    ncs,
    ack,SIN,SCL,SNCS);
input clk;
input rst;
input ncs;
input [9:0]wr_data;
output ack;
output SIN,SCL,SNCS;


reg [9:0]reg_data;
reg    SIN,SCL,SNCS;
reg    ack;
reg [1:0]acter;
reg [3:0]scounter;
reg[8:0] cter;    //31count
reg clk250,clk250_d; //32 divider  clk250 rising
reg ncs_d,scl_d;
reg sncs_d;

always @(posedge clk or posedge rst)
        if(rst) cter<=9'h000;
        //else if(cter<9'h01) cter<=cter+9'h001;
        //else if(cter==9'h01) cter<=9'h000;
        else if(cter<9'h01f) cter<=cter+9'h001;
        else if(cter==9'h01f) cter<=9'h000;
        else cter<=cter;

always @(posedge clk or posedge rst)
        if(rst) clk250<=1'b0;
        //else if(cter==9'h01) clk250<=~clk250;
        else if(cter==9'h01f) clk250<=~clk250;
        else clk250<=clk250;

always @(posedge clk or posedge rst)
        if(rst) clk250_d<=0;
        else clk250_d<=clk250;
        
        
wire clk250_r=clk250 & ~clk250_d; //capture the rising edge clk250
wire clk250_f=~clk250 & clk250_d; //capture the falling edge clk250

always @(posedge clk or posedge rst)
        if(rst) ncs_d<=1'b1;
        else ncs_d<=ncs;
        
wire ncs_r=ncs & ~ncs_d;
wire ncs_f=~ncs & ncs_d;  

always @(posedge clk or posedge rst)
        if(rst)SCL<=1'b1;
        else if(SNCS) SCL<=1'b1;
        else if(clk250_r && !SNCS)SCL<=1'b1;
        else if(clk250_f && !SNCS)SCL<=1'b0;
        else SCL<=SCL;
      //the preiod of SCL=clk250 
always @(posedge clk or posedge rst)
        if(rst) scl_d<=1'b0;
        else scl_d<=SCL;  
             
wire scl_f=~SCL && scl_d;
wire scl_r=SCL && ~scl_d; 

always @(posedge clk or posedge rst)
        if(rst)  reg_data<=10'h000;
        else if(ncs_f && SNCS) reg_data<=wr_data;
        else if(!SNCS && scl_r) reg_data[9:0]={reg_data[8:0],1'b1};
        //reg_data shift left one bit
        else reg_data<=reg_data;
        
always @(posedge clk or posedge rst)
        if(rst) SNCS<=1'b1;
        else if(ncs_r && SNCS) SNCS<=1'b0;
        else if(scounter==4'hd)SNCS<=1'b1;
        else SNCS<=SNCS;

//always @(posedge clk or posedge rst)
//        if(rst) sncs_d<=1'b1;
//        else sncs_d<=SNCS;
              
//wire sncs_r=SNCS & sncs_d;



always @(posedge clk or posedge rst)
        if(rst)scounter<=4'h0;
        else if(SNCS) scounter<=4'h0;
        else if(!SNCS && scl_f) scounter<=scounter+4'h1;
        else if(scounter>=4'hd)scounter<=4'he;
        else scounter<=scounter;

//scounter  SCL pulse counter

always @(posedge clk or posedge rst)
        if(rst) SIN<=1'b1;
        else if(SNCS) SIN<=1'b1;        
        else if(!SNCS && scl_f && (scounter<4'ha)) SIN<=reg_data[9];
        else if(scl_f && (scounter>=4'ha)) SIN<=1'b1;
        else SIN<=SIN;
        
 //the following two always may unused       
       
always @(posedge clk or posedge rst)
        if(rst) ack<=0;
        else if(scounter==4'hd) ack<=1'b1;
        else if(acter==2'h3)ack<=1'b0;
        else ack<=ack;
        
 

always @(posedge clk or posedge rst)
        if(rst) acter<=2'h0;
        else if(ack) acter<=acter+1'b1;
        else if(ack && acter==2'h3)acter<=0;
        //else if(acter==2'h3)acter<=acter;
        else acter<=acter;
        
               
                  

endmodule		

module sin_rom(clk,addr,data);
input clk;
input [5:0] addr;
output [9:0] data;
reg [9:0] data;

always@(posedge clk) begin
      case (addr)
           6'h00	: data<=10'h200;
	         6'h01	: data<=10'h232;
	6'h02	: data<=10'h263;
	6'h03	: data<=10'h294;
	6'h04	: data<=10'h2c3;
	6'h05	: data<=10'h2f1;
	6'h06	: data<=10'h31c;
	6'h07	: data<=10'h344;
	6'h08	: data<=10'h36a;
	6'h09	: data<=10'h38b;
	6'h0a	: data<=10'h3a9;
	6'h0b	: data<=10'h3c3;
	6'h0c	: data<=10'h3d9;
	6'h0d	: data<=10'h3e9;
	6'h0e	: data<=10'h3f6;
	6'h0f	: data<=10'h3fd;
	6'h10	: data<=10'h3ff;
	6'h11	: data<=10'h3fd;
	6'h12	: data<=10'h3f6;
	6'h13	: data<=10'h3e9;
	6'h14	: data<=10'h3d9;
	6'h15	: data<=10'h3c3;
	6'h16	: data<=10'h3a9;
	6'h17	: data<=10'h38b;
	6'h18	: data<=10'h36a;
	6'h19	: data<=10'h344;
	6'h1a	: data<=10'h31c;
	6'h1b	: data<=10'h2f1;
	6'h1c	: data<=10'h2c3;
	6'h1d	: data<=10'h294;
	6'h1e	: data<=10'h263;
	6'h1f	: data<=10'h232;
	6'h20	: data<=10'h1ff;
	6'h21	: data<=10'h1cd;
	6'h22	: data<=10'h19c;
	6'h23	: data<=10'h16b;
	6'h24	: data<=10'h13c;
	6'h25	: data<=10'h10e;
	6'h26	: data<=10'h0e3;
	6'h27	: data<=10'h0bb;
	6'h28	: data<=10'h095;
	6'h29	: data<=10'h074;
	6'h2a	: data<=10'h056;
	6'h2b	: data<=10'h03c;
	6'h2c	: data<=10'h026;
	6'h2d	: data<=10'h016;
	6'h2e	: data<=10'h009;
	6'h2f	: data<=10'h002;
	6'h30	: data<=10'h000;
	6'h31	: data<=10'h002;
	6'h32	: data<=10'h009;
	6'h33	: data<=10'h016;
	6'h34	: data<=10'h026;
	6'h35	: data<=10'h03c;
	6'h36	: data<=10'h056;
	6'h37	: data<=10'h074;
	6'h38	: data<=10'h095;
	6'h39	: data<=10'h0bb;
	6'h3a	: data<=10'h0e3;
	6'h3b	: data<=10'h10e;
	6'h3c	: data<=10'h13c;
	6'h3d	: data<=10'h16b;
	6'h3e	: data<=10'h19c;
	6'h3f	: data<=10'h1cd;
	
 endcase
     
end
endmodule