alu.tan.rpt

设计带进位算术逻辑运算单元

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Mon Apr 20 15:13:42 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off alu -c alu --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "74373b:inst2|19" is a latch
    Warning: Node "74373b:inst1|19" is a latch
    Warning: Node "74373b:inst1|18" is a latch
    Warning: Node "74373b:inst2|18" is a latch
    Warning: Node "74373b:inst1|16" is a latch
    Warning: Node "74373b:inst2|16" is a latch
    Warning: Node "74373b:inst2|17" is a latch
    Warning: Node "74373b:inst1|17" is a latch
    Warning: Node "74373b:inst1|15" is a latch
    Warning: Node "74373b:inst2|15" is a latch
    Warning: Node "74373b:inst1|14" is a latch
    Warning: Node "74373b:inst2|14" is a latch
    Warning: Node "74373b:inst1|13" is a latch
    Warning: Node "74373b:inst2|13" is a latch
    Warning: Node "74373b:inst1|12" is a latch
    Warning: Node "74373b:inst2|12" is a latch
Warning: Found combinational loop of 7 nodes
    Warning: Node "alu181:inst5|Mux0~492"
    Warning: Node "alu181:inst5|Add2~45"
    Warning: Node "alu181:inst5|Mux0~479"
    Warning: Node "alu181:inst5|Mux0~487"
    Warning: Node "alu181:inst5|Mux0~488"
    Warning: Node "alu181:inst5|Mux0~490"
    Warning: Node "alu181:inst5|Mux0~491"
Warning: Found combinational loop of 7 nodes
    Warning: Node "alu181:inst5|Mux1~90"
    Warning: Node "alu181:inst5|Add2~47"
    Warning: Node "alu181:inst5|Mux1~81"
    Warning: Node "alu181:inst5|Mux1~86"
    Warning: Node "alu181:inst5|Mux1~87"
    Warning: Node "alu181:inst5|Mux1~88"
    Warning: Node "alu181:inst5|Mux1~89"
Warning: Found combinational loop of 7 nodes
    Warning: Node "alu181:inst5|Mux2~90"
    Warning: Node "alu181:inst5|Add2~49"
    Warning: Node "alu181:inst5|Mux2~81"
    Warning: Node "alu181:inst5|Mux2~86"
    Warning: Node "alu181:inst5|Mux2~87"
    Warning: Node "alu181:inst5|Mux2~88"
    Warning: Node "alu181:inst5|Mux2~89"
Warning: Found combinational loop of 7 nodes
    Warning: Node "alu181:inst5|Mux3~90"
    Warning: Node "alu181:inst5|Add2~51"
    Warning: Node "alu181:inst5|Mux3~81"
    Warning: Node "alu181:inst5|Mux3~86"
    Warning: Node "alu181:inst5|Mux3~87"
    Warning: Node "alu181:inst5|Mux3~88"
    Warning: Node "alu181:inst5|Mux3~89"
Warning: Found combinational loop of 7 nodes
    Warning: Node "alu181:inst5|Mux4~90"
    Warning: Node "alu181:inst5|Add2~53"
    Warning: Node "alu181:inst5|Mux4~81"
    Warning: Node "alu181:inst5|Mux4~86"
    Warning: Node "alu181:inst5|Mux4~87"
    Warning: Node "alu181:inst5|Mux4~88"
    Warning: Node "alu181:inst5|Mux4~89"
Warning: Found combinational loop of 7 nodes
    Warning: Node "alu181:inst5|Mux5~90"
    Warning: Node "alu181:inst5|Add2~55"
    Warning: Node "alu181:inst5|Mux5~81"
    Warning: Node "alu181:inst5|Mux5~86"
    Warning: Node "alu181:inst5|Mux5~87"
    Warning: Node "alu181:inst5|Mux5~88"
    Warning: Node "alu181:inst5|Mux5~89"
Warning: Found combinational loop of 7 nodes
    Warning: Node "alu181:inst5|Mux6~90"
    Warning: Node "alu181:inst5|Add2~57"
    Warning: Node "alu181:inst5|Mux6~81"
    Warning: Node "alu181:inst5|Mux6~86"
    Warning: Node "alu181:inst5|Mux6~87"
    Warning: Node "alu181:inst5|Mux6~88"
    Warning: Node "alu181:inst5|Mux6~89"
Warning: Found combinational loop of 4 nodes
    Warning: Node "alu181:inst5|Mux7~147"
    Warning: Node "alu181:inst5|Add2~59"
    Warning: Node "alu181:inst5|F~1358"
    Warning: Node "alu181:inst5|Mux7~139"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "sclk" is an undefined clock
    Info: Assuming node "bclk" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "aclk" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Clock "sclk" Internal fmax is restricted to 275.03 MHz between source register "lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1]" and destination register "lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.040 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y18_N6; Fanout = 35; REG Node = 'lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1]'
            Info: 2: + IC(0.598 ns) + CELL(0.575 ns) = 1.173 ns; Loc. = LC_X14_Y18_N6; Fanout = 2; COMB Node = 'lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1'
            Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.253 ns; Loc. = LC_X14_Y18_N7; Fanout = 1; COMB Node = 'lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1'
            Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 2.040 ns; Loc. = LC_X14_Y18_N8; Fanout = 25; REG Node = 'lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3]'
            Info: Total cell delay = 1.442 ns ( 70.69 % )
            Info: Total interconnect delay = 0.598 ns ( 29.31 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "sclk" to destination register is 3.246 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'sclk'
                Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X14_Y18_N8; Fanout = 25; REG Node = 'lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3]'
                Info: Total cell delay = 2.180 ns ( 67.16 % )
                Info: Total interconnect delay = 1.066 ns ( 32.84 % )
            Info: - Longest clock path from clock "sclk" to source register is 3.246 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'sclk'
                Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X14_Y18_N6; Fanout = 35; REG Node = 'lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1]'
                Info: Total cell delay = 2.180 ns ( 67.16 % )
                Info: Total interconnect delay = 1.066 ns ( 32.84 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "74373b:inst2|12" (data pin = "IN[1]", clock pin = "bclk") is 7.324 ns
    Info: + Longest pin to register delay is 8.843 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_79; Fanout = 2; PIN Node = 'IN[1]'
        Info: 2: + IC(6.778 ns) + CELL(0.590 ns) = 8.843 ns; Loc. = LC_X12_Y19_N9; Fanout = 13; REG Node = '74373b:inst2|12'
        Info: Total cell delay = 2.065 ns ( 23.35 % )
        Info: Total interconnect delay = 6.778 ns ( 76.65 % )
    Info: + Micro setup delay of destination is 1.864 ns
    Info: - Shortest clock path from clock "bclk" to destination register is 3.383 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'bclk'