exercise_5_3_4_3.map.summary

CLK 为其时钟脉冲 M 控制工作模式 CO 为允许带进位移位输入 S 控制移位模式0-3 D[7..0]是移位数据输入 QB[7..0]是移位数据输出 CN是移位数

Analysis & Synthesis Status : Successful - Sat Apr 25 16:12:03 2009
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : EXERCISE_5_3_4_3
Top-level Entity Name : EXERCISE_5_3_4_3
Family : Cyclone
Total logic elements : 1,258
Total pins : 79
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge