📄 exercise_5_3_4_3.map.rpt
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------------------+
; ALU.v ; yes ; User Verilog HDL File ; D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v ;
; EXERCISE_5_3_4_3.bdf ; yes ; User Block Diagram/Schematic File ; D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/EXERCISE_5_3_4_3.bdf ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 1258 ;
; -- Combinational with no register ; 1258 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 0 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 570 ;
; -- 3 input functions ; 330 ;
; -- 2 input functions ; 301 ;
; -- 1 input functions ; 57 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 834 ;
; -- arithmetic mode ; 424 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; Total logic cells in carry chains ; 477 ;
; I/O pins ; 79 ;
; Maximum fan-out node ; S[3] ;
; Maximum fan-out ; 156 ;
; Total fan-out ; 3954 ;
; Average fan-out ; 2.96 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
; |EXERCISE_5_3_4_3 ; 1258 (0) ; 0 ; 0 ; 79 ; 0 ; 1258 (0) ; 0 (0) ; 0 (0) ; 477 (0) ; 0 (0) ; |EXERCISE_5_3_4_3 ; work ;
; |ALU:inst1| ; 456 (456) ; 0 ; 0 ; 0 ; 0 ; 456 (456) ; 0 (0) ; 0 (0) ; 189 (189) ; 0 (0) ; |EXERCISE_5_3_4_3|ALU:inst1 ; work ;
; |ALU:inst2| ; 362 (362) ; 0 ; 0 ; 0 ; 0 ; 362 (362) ; 0 (0) ; 0 (0) ; 99 (99) ; 0 (0) ; |EXERCISE_5_3_4_3|ALU:inst2 ; work ;
; |ALU:inst| ; 440 (440) ; 0 ; 0 ; 0 ; 0 ; 440 (440) ; 0 (0) ; 0 (0) ; 189 (189) ; 0 (0) ; |EXERCISE_5_3_4_3|ALU:inst ; work ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |EXERCISE_5_3_4_3|ALU:inst2|Mux11 ;
; 7:1 ; 8 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |EXERCISE_5_3_4_3|ALU:inst2|Add0 ;
; 36:1 ; 7 bits ; 168 LEs ; 112 LEs ; 56 LEs ; No ; |EXERCISE_5_3_4_3|ALU:inst2|F[1] ;
; 46:1 ; 7 bits ; 210 LEs ; 168 LEs ; 42 LEs ; No ; |EXERCISE_5_3_4_3|ALU:inst|F[2] ;
; 46:1 ; 7 bits ; 210 LEs ; 168 LEs ; 42 LEs ; No ; |EXERCISE_5_3_4_3|ALU:inst1|F[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Sat Apr 25 16:11:49 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EXERCISE_5_3_4_3 -c EXERCISE_5_3_4_3
Info: Found 1 design units, including 1 entities, in source file ALU.v
Info: Found entity 1: ALU
Info: Found 1 design units, including 1 entities, in source file EXERCISE_5_3_4_3.bdf
Info: Found entity 1: EXERCISE_5_3_4_3
Info: Elaborating entity "EXERCISE_5_3_4_3" for the top level hierarchy
Info: Elaborating entity "ALU" for hierarchy "ALU:inst2"
Warning (10240): Verilog HDL Always Construct warning at ALU.v(12): inferring latch(es) for variable "MEDI", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "MEDI[0]" at ALU.v(35)
Info (10041): Inferred latch for "MEDI[1]" at ALU.v(35)
Info (10041): Inferred latch for "MEDI[2]" at ALU.v(35)
Info (10041): Inferred latch for "MEDI[3]" at ALU.v(35)
Info (10041): Inferred latch for "MEDI[4]" at ALU.v(35)
Info (10041): Inferred latch for "MEDI[5]" at ALU.v(35)
Info (10041): Inferred latch for "MEDI[6]" at ALU.v(35)
Info (10041): Inferred latch for "MEDI[7]" at ALU.v(35)
Info (10041): Inferred latch for "MEDI[8]" at ALU.v(35)
Info: Implemented 1337 device resources after synthesis - the final resource count might be different
Info: Implemented 54 input pins
Info: Implemented 25 output pins
Info: Implemented 1258 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 137 megabytes of memory during processing
Info: Processing ended: Sat Apr 25 16:12:03 2009
Info: Elapsed time: 00:00:14
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