shifter.tan.summary

移位运算器SHIFTER 使用Verilog HDL 语言编写

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.133 ns
From           : d[7]
To             : cn$latch
From Clock     : --
To Clock       : s[0]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.809 ns
From           : cn$latch
To             : cn
From Clock     : m
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 18.427 ns
From           : d[3]
To             : qb[5]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.675 ns
From           : d[0]
To             : cn$latch
From Clock     : --
To Clock       : m
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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