shifter.tan.qmsg

移位运算器SHIFTER 使用Verilog HDL 语言编写

{ "Info" "ITDB_TSU_RESULT" "cn\$latch d\[7\] s\[0\] 6.133 ns register " "Info: tsu for register \"cn\$latch\" (data pin = \"d\[7\]\", clock pin = \"s\[0\]\") is 6.133 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.726 ns + Longest pin register " "Info: + Longest pin to register delay is 8.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns d\[7\] 1 PIN PIN_228 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_228; Fanout = 5; PIN Node = 'd\[7\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[7] } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.932 ns) + CELL(0.590 ns) 7.997 ns Mux8~6 2 COMB LC_X10_Y20_N4 1 " "Info: 2: + IC(5.932 ns) + CELL(0.590 ns) = 7.997 ns; Loc. = LC_X10_Y20_N4; Fanout = 1; COMB Node = 'Mux8~6'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "6.522 ns" { d[7] Mux8~6 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.292 ns) 8.726 ns cn\$latch 3 REG LC_X10_Y20_N3 1 " "Info: 3: + IC(0.437 ns) + CELL(0.292 ns) = 8.726 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn\$latch'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.729 ns" { Mux8~6 cn$latch } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.357 ns ( 27.01 % ) " "Info: Total cell delay = 2.357 ns ( 27.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.369 ns ( 72.99 % ) " "Info: Total interconnect delay = 6.369 ns ( 72.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "8.726 ns" { d[7] Mux8~6 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.726 ns" { d[7] {} d[7]~out0 {} Mux8~6 {} cn$latch {} } { 0.000ns 0.000ns 5.932ns 0.437ns } { 0.000ns 1.475ns 0.590ns 0.292ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.960 ns + " "Info: + Micro setup delay of destination is 0.960 ns" {  } { { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "s\[0\] destination 3.553 ns - Shortest register " "Info: - Shortest clock path from clock \"s\[0\]\" to destination register is 3.553 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns s\[0\] 1 CLK PIN_225 13 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_225; Fanout = 13; CLK Node = 's\[0\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { s[0] } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.668 ns) + CELL(0.114 ns) 3.257 ns Mux9~13 2 COMB LC_X10_Y20_N2 1 " "Info: 2: + IC(1.668 ns) + CELL(0.114 ns) = 3.257 ns; Loc. = LC_X10_Y20_N2; Fanout = 1; COMB Node = 'Mux9~13'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.782 ns" { s[0] Mux9~13 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.553 ns cn\$latch 3 REG LC_X10_Y20_N3 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 3.553 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn\$latch'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux9~13 cn$latch } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.703 ns ( 47.93 % ) " "Info: Total cell delay = 1.703 ns ( 47.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.850 ns ( 52.07 % ) " "Info: Total interconnect delay = 1.850 ns ( 52.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.553 ns" { s[0] Mux9~13 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.553 ns" { s[0] {} s[0]~out0 {} Mux9~13 {} cn$latch {} } { 0.000ns 0.000ns 1.668ns 0.182ns } { 0.000ns 1.475ns 0.114ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "8.726 ns" { d[7] Mux8~6 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.726 ns" { d[7] {} d[7]~out0 {} Mux8~6 {} cn$latch {} } { 0.000ns 0.000ns 5.932ns 0.437ns } { 0.000ns 1.475ns 0.590ns 0.292ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.553 ns" { s[0] Mux9~13 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.553 ns" { s[0] {} s[0]~out0 {} Mux9~13 {} cn$latch {} } { 0.000ns 0.000ns 1.668ns 0.182ns } { 0.000ns 1.475ns 0.114ns 0.114ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "m cn cn\$latch 9.809 ns register " "Info: tco from clock \"m\" to destination pin \"cn\" through register \"cn\$latch\" is 9.809 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "m source 5.243 ns + Longest register " "Info: + Longest clock path from clock \"m\" to source register is 5.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns m 1 CLK PIN_75 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_75; Fanout = 3; CLK Node = 'm'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { m } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.030 ns) + CELL(0.442 ns) 4.947 ns Mux9~13 2 COMB LC_X10_Y20_N2 1 " "Info: 2: + IC(3.030 ns) + CELL(0.442 ns) = 4.947 ns; Loc. = LC_X10_Y20_N2; Fanout = 1; COMB Node = 'Mux9~13'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.472 ns" { m Mux9~13 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 5.243 ns cn\$latch 3 REG LC_X10_Y20_N3 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 5.243 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn\$latch'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux9~13 cn$latch } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.031 ns ( 38.74 % ) " "Info: Total cell delay = 2.031 ns ( 38.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.212 ns ( 61.26 % ) " "Info: Total interconnect delay = 3.212 ns ( 61.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.243 ns" { m Mux9~13 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.243 ns" { m {} m~out0 {} Mux9~13 {} cn$latch {} } { 0.000ns 0.000ns 3.030ns 0.182ns } { 0.000ns 1.475ns 0.442ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.566 ns + Longest register pin " "Info: + Longest register to pin delay is 4.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cn\$latch 1 REG LC_X10_Y20_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn\$latch'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { cn$latch } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.442 ns) + CELL(2.124 ns) 4.566 ns cn 2 PIN PIN_17 0 " "Info: 2: + IC(2.442 ns) + CELL(2.124 ns) = 4.566 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'cn'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.566 ns" { cn$latch cn } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 46.52 % ) " "Info: Total cell delay = 2.124 ns ( 46.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.442 ns ( 53.48 % ) " "Info: Total interconnect delay = 2.442 ns ( 53.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.566 ns" { cn$latch cn } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "4.566 ns" { cn$latch {} cn {} } { 0.000ns 2.442ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.243 ns" { m Mux9~13 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.243 ns" { m {} m~out0 {} Mux9~13 {} cn$latch {} } { 0.000ns 0.000ns 3.030ns 0.182ns } { 0.000ns 1.475ns 0.442ns 0.114ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "4.566 ns" { cn$latch cn } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "4.566 ns" { cn$latch {} cn {} } { 0.000ns 2.442ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "d\[3\] qb\[5\] 18.427 ns Longest " "Info: Longest tpd from source pin \"d\[3\]\" to destination pin \"qb\[5\]\" is 18.427 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns d\[3\] 1 PIN PIN_156 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_156; Fanout = 6; PIN Node = 'd\[3\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[3] } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.869 ns) + CELL(0.564 ns) 10.902 ns Add0~44 2 COMB LC_X10_Y15_N3 2 " "Info: 2: + IC(8.869 ns) + CELL(0.564 ns) = 10.902 ns; Loc. = LC_X10_Y15_N3; Fanout = 2; COMB Node = 'Add0~44'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "9.433 ns" { d[3] Add0~44 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 11.080 ns Add0~46 3 COMB LC_X10_Y15_N4 3 " "Info: 3: + IC(0.000 ns) + CELL(0.178 ns) = 11.080 ns; Loc. = LC_X10_Y15_N4; Fanout = 3; COMB Node = 'Add0~46'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Add0~44 Add0~46 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 11.701 ns Add0~47 4 COMB LC_X10_Y15_N5 1 " "Info: 4: + IC(0.000 ns) + CELL(0.621 ns) = 11.701 ns; Loc. = LC_X10_Y15_N5; Fanout = 1; COMB Node = 'Add0~47'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { Add0~46 Add0~47 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.442 ns) 13.356 ns Mux2~4 5 COMB LC_X10_Y14_N9 1 " "Info: 5: + IC(1.213 ns) + CELL(0.442 ns) = 13.356 ns; Loc. = LC_X10_Y14_N9; Fanout = 1; COMB Node = 'Mux2~4'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.655 ns" { Add0~47 Mux2~4 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.963 ns) + CELL(2.108 ns) 18.427 ns qb\[5\] 6 PIN PIN_79 0 " "Info: 6: + IC(2.963 ns) + CELL(2.108 ns) = 18.427 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'qb\[5\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.071 ns" { Mux2~4 qb[5] } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.382 ns ( 29.21 % ) " "Info: Total cell delay = 5.382 ns ( 29.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.045 ns ( 70.79 % ) " "Info: Total interconnect delay = 13.045 ns ( 70.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "18.427 ns" { d[3] Add0~44 Add0~46 Add0~47 Mux2~4 qb[5] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "18.427 ns" { d[3] {} d[3]~out0 {} Add0~44 {} Add0~46 {} Add0~47 {} Mux2~4 {} qb[5] {} } { 0.000ns 0.000ns 8.869ns 0.000ns 0.000ns 1.213ns 2.963ns } { 0.000ns 1.469ns 0.564ns 0.178ns 0.621ns 0.442ns 2.108ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "cn\$latch d\[0\] m -2.675 ns register " "Info: th for register \"cn\$latch\" (data pin = \"d\[0\]\", clock pin = \"m\") is -2.675 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "m destination 5.243 ns + Longest register " "Info: + Longest clock path from clock \"m\" to destination register is 5.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns m 1 CLK PIN_75 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_75; Fanout = 3; CLK Node = 'm'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { m } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.030 ns) + CELL(0.442 ns) 4.947 ns Mux9~13 2 COMB LC_X10_Y20_N2 1 " "Info: 2: + IC(3.030 ns) + CELL(0.442 ns) = 4.947 ns; Loc. = LC_X10_Y20_N2; Fanout = 1; COMB Node = 'Mux9~13'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.472 ns" { m Mux9~13 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 5.243 ns cn\$latch 3 REG LC_X10_Y20_N3 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 5.243 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn\$latch'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Mux9~13 cn$latch } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.031 ns ( 38.74 % ) " "Info: Total cell delay = 2.031 ns ( 38.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.212 ns ( 61.26 % ) " "Info: Total interconnect delay = 3.212 ns ( 61.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.243 ns" { m Mux9~13 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.243 ns" { m {} m~out0 {} Mux9~13 {} cn$latch {} } { 0.000ns 0.000ns 3.030ns 0.182ns } { 0.000ns 1.475ns 0.442ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.918 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.918 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns d\[0\] 1 PIN PIN_223 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_223; Fanout = 7; PIN Node = 'd\[0\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[0] } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.600 ns) + CELL(0.114 ns) 7.189 ns Mux8~6 2 COMB LC_X10_Y20_N4 1 " "Info: 2: + IC(5.600 ns) + CELL(0.114 ns) = 7.189 ns; Loc. = LC_X10_Y20_N4; Fanout = 1; COMB Node = 'Mux8~6'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.714 ns" { d[0] Mux8~6 } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.292 ns) 7.918 ns cn\$latch 3 REG LC_X10_Y20_N3 1 " "Info: 3: + IC(0.437 ns) + CELL(0.292 ns) = 7.918 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn\$latch'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.729 ns" { Mux8~6 cn$latch } "NODE_NAME" } } { "shifter.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/shifter/shifter.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.881 ns ( 23.76 % ) " "Info: Total cell delay = 1.881 ns ( 23.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.037 ns ( 76.24 % ) " "Info: Total interconnect delay = 6.037 ns ( 76.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "7.918 ns" { d[0] Mux8~6 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "7.918 ns" { d[0] {} d[0]~out0 {} Mux8~6 {} cn$latch {} } { 0.000ns 0.000ns 5.600ns 0.437ns } { 0.000ns 1.475ns 0.114ns 0.292ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "5.243 ns" { m Mux9~13 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "5.243 ns" { m {} m~out0 {} Mux9~13 {} cn$latch {} } { 0.000ns 0.000ns 3.030ns 0.182ns } { 0.000ns 1.475ns 0.442ns 0.114ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "7.918 ns" { d[0] Mux8~6 cn$latch } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "7.918 ns" { d[0] {} d[0]~out0 {} Mux8~6 {} cn$latch {} } { 0.000ns 0.000ns 5.600ns 0.437ns } { 0.000ns 1.475ns 0.114ns 0.292ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 19 10:47:45 2009 " "Info: Processing ended: Sun Apr 19 10:47:45 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}