shifter.tan.rpt

移位运算器SHIFTER 使用Verilog HDL 语言编写

; N/A   ; None              ; 15.566 ns       ; d[1] ; qb[1] ;
; N/A   ; None              ; 15.522 ns       ; d[4] ; qb[6] ;
; N/A   ; None              ; 15.429 ns       ; co   ; qb[3] ;
; N/A   ; None              ; 15.417 ns       ; d[5] ; qb[7] ;
; N/A   ; None              ; 15.415 ns       ; d[0] ; qb[6] ;
; N/A   ; None              ; 15.415 ns       ; d[2] ; qb[3] ;
; N/A   ; None              ; 15.373 ns       ; d[6] ; qb[7] ;
; N/A   ; None              ; 15.372 ns       ; co   ; qb[1] ;
; N/A   ; None              ; 15.361 ns       ; co   ; qb[7] ;
; N/A   ; None              ; 15.351 ns       ; d[2] ; qb[7] ;
; N/A   ; None              ; 15.342 ns       ; d[3] ; qb[2] ;
; N/A   ; None              ; 15.286 ns       ; d[4] ; qb[4] ;
; N/A   ; None              ; 15.265 ns       ; co   ; qb[4] ;
; N/A   ; None              ; 15.251 ns       ; d[2] ; qb[4] ;
; N/A   ; None              ; 15.138 ns       ; d[6] ; qb[6] ;
; N/A   ; None              ; 14.962 ns       ; d[0] ; qb[0] ;
; N/A   ; None              ; 14.957 ns       ; d[5] ; qb[5] ;
; N/A   ; None              ; 14.928 ns       ; co   ; qb[6] ;
; N/A   ; None              ; 14.918 ns       ; d[2] ; qb[6] ;
; N/A   ; None              ; 14.904 ns       ; d[5] ; qb[6] ;
; N/A   ; None              ; 14.846 ns       ; d[1] ; qb[2] ;
; N/A   ; None              ; 14.827 ns       ; d[7] ; qb[7] ;
; N/A   ; None              ; 14.623 ns       ; d[0] ; qb[2] ;
; N/A   ; None              ; 14.468 ns       ; co   ; qb[0] ;
; N/A   ; None              ; 14.382 ns       ; s[1] ; qb[1] ;
; N/A   ; None              ; 14.379 ns       ; s[0] ; qb[1] ;
; N/A   ; None              ; 14.369 ns       ; s[1] ; qb[3] ;
; N/A   ; None              ; 14.317 ns       ; d[7] ; qb[6] ;
; N/A   ; None              ; 14.238 ns       ; s[1] ; qb[7] ;
; N/A   ; None              ; 14.231 ns       ; s[0] ; qb[7] ;
; N/A   ; None              ; 14.191 ns       ; s[1] ; qb[5] ;
; N/A   ; None              ; 14.181 ns       ; s[1] ; qb[4] ;
; N/A   ; None              ; 14.134 ns       ; co   ; qb[2] ;
; N/A   ; None              ; 14.129 ns       ; s[0] ; qb[3] ;
; N/A   ; None              ; 14.049 ns       ; m    ; qb[0] ;
; N/A   ; None              ; 13.965 ns       ; s[0] ; qb[5] ;
; N/A   ; None              ; 13.965 ns       ; s[0] ; qb[4] ;
; N/A   ; None              ; 13.834 ns       ; s[1] ; qb[6] ;
; N/A   ; None              ; 13.828 ns       ; s[0] ; qb[6] ;
; N/A   ; None              ; 13.814 ns       ; d[5] ; qb[4] ;
; N/A   ; None              ; 13.642 ns       ; s[1] ; qb[2] ;
; N/A   ; None              ; 13.615 ns       ; d[7] ; qb[0] ;
; N/A   ; None              ; 13.602 ns       ; d[2] ; qb[2] ;
; N/A   ; None              ; 13.538 ns       ; d[6] ; qb[5] ;
; N/A   ; None              ; 13.291 ns       ; d[4] ; qb[3] ;
; N/A   ; None              ; 13.095 ns       ; d[1] ; qb[0] ;
; N/A   ; None              ; 13.087 ns       ; d[2] ; qb[1] ;
; N/A   ; None              ; 12.924 ns       ; s[0] ; qb[2] ;
; N/A   ; None              ; 12.642 ns       ; s[0] ; qb[0] ;
; N/A   ; None              ; 12.641 ns       ; s[1] ; qb[0] ;
+-------+-------------------+-----------------+------+-------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -2.675 ns ; d[0] ; cn$latch ; m        ;
; N/A           ; None        ; -2.992 ns ; s[0] ; cn$latch ; m        ;
; N/A           ; None        ; -3.483 ns ; d[7] ; cn$latch ; m        ;
; N/A           ; None        ; -4.031 ns ; d[0] ; cn$latch ; s[1]     ;
; N/A           ; None        ; -4.348 ns ; s[0] ; cn$latch ; s[1]     ;
; N/A           ; None        ; -4.365 ns ; d[0] ; cn$latch ; s[0]     ;
; N/A           ; None        ; -4.682 ns ; s[0] ; cn$latch ; s[0]     ;
; N/A           ; None        ; -4.839 ns ; d[7] ; cn$latch ; s[1]     ;
; N/A           ; None        ; -5.173 ns ; d[7] ; cn$latch ; s[0]     ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Sun Apr 19 10:47:45 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shifter -c shifter --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "cn$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "s[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "s[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "m" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Mux9~13" as buffer
Info: tsu for register "cn$latch" (data pin = "d[7]", clock pin = "s[0]") is 6.133 ns
    Info: + Longest pin to register delay is 8.726 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_228; Fanout = 5; PIN Node = 'd[7]'
        Info: 2: + IC(5.932 ns) + CELL(0.590 ns) = 7.997 ns; Loc. = LC_X10_Y20_N4; Fanout = 1; COMB Node = 'Mux8~6'
        Info: 3: + IC(0.437 ns) + CELL(0.292 ns) = 8.726 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn$latch'
        Info: Total cell delay = 2.357 ns ( 27.01 % )
        Info: Total interconnect delay = 6.369 ns ( 72.99 % )
    Info: + Micro setup delay of destination is 0.960 ns
    Info: - Shortest clock path from clock "s[0]" to destination register is 3.553 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_225; Fanout = 13; CLK Node = 's[0]'
        Info: 2: + IC(1.668 ns) + CELL(0.114 ns) = 3.257 ns; Loc. = LC_X10_Y20_N2; Fanout = 1; COMB Node = 'Mux9~13'
        Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 3.553 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn$latch'
        Info: Total cell delay = 1.703 ns ( 47.93 % )
        Info: Total interconnect delay = 1.850 ns ( 52.07 % )
Info: tco from clock "m" to destination pin "cn" through register "cn$latch" is 9.809 ns
    Info: + Longest clock path from clock "m" to source register is 5.243 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_75; Fanout = 3; CLK Node = 'm'
        Info: 2: + IC(3.030 ns) + CELL(0.442 ns) = 4.947 ns; Loc. = LC_X10_Y20_N2; Fanout = 1; COMB Node = 'Mux9~13'
        Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 5.243 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn$latch'
        Info: Total cell delay = 2.031 ns ( 38.74 % )
        Info: Total interconnect delay = 3.212 ns ( 61.26 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.566 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn$latch'
        Info: 2: + IC(2.442 ns) + CELL(2.124 ns) = 4.566 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'cn'
        Info: Total cell delay = 2.124 ns ( 46.52 % )
        Info: Total interconnect delay = 2.442 ns ( 53.48 % )
Info: Longest tpd from source pin "d[3]" to destination pin "qb[5]" is 18.427 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_156; Fanout = 6; PIN Node = 'd[3]'
    Info: 2: + IC(8.869 ns) + CELL(0.564 ns) = 10.902 ns; Loc. = LC_X10_Y15_N3; Fanout = 2; COMB Node = 'Add0~44'
    Info: 3: + IC(0.000 ns) + CELL(0.178 ns) = 11.080 ns; Loc. = LC_X10_Y15_N4; Fanout = 3; COMB Node = 'Add0~46'
    Info: 4: + IC(0.000 ns) + CELL(0.621 ns) = 11.701 ns; Loc. = LC_X10_Y15_N5; Fanout = 1; COMB Node = 'Add0~47'
    Info: 5: + IC(1.213 ns) + CELL(0.442 ns) = 13.356 ns; Loc. = LC_X10_Y14_N9; Fanout = 1; COMB Node = 'Mux2~4'
    Info: 6: + IC(2.963 ns) + CELL(2.108 ns) = 18.427 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'qb[5]'
    Info: Total cell delay = 5.382 ns ( 29.21 % )
    Info: Total interconnect delay = 13.045 ns ( 70.79 % )
Info: th for register "cn$latch" (data pin = "d[0]", clock pin = "m") is -2.675 ns
    Info: + Longest clock path from clock "m" to destination register is 5.243 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_75; Fanout = 3; CLK Node = 'm'
        Info: 2: + IC(3.030 ns) + CELL(0.442 ns) = 4.947 ns; Loc. = LC_X10_Y20_N2; Fanout = 1; COMB Node = 'Mux9~13'
        Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 5.243 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn$latch'
        Info: Total cell delay = 2.031 ns ( 38.74 % )
        Info: Total interconnect delay = 3.212 ns ( 61.26 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 7.918 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_223; Fanout = 7; PIN Node = 'd[0]'
        Info: 2: + IC(5.600 ns) + CELL(0.114 ns) = 7.189 ns; Loc. = LC_X10_Y20_N4; Fanout = 1; COMB Node = 'Mux8~6'
        Info: 3: + IC(0.437 ns) + CELL(0.292 ns) = 7.918 ns; Loc. = LC_X10_Y20_N3; Fanout = 1; REG Node = 'cn$latch'
        Info: Total cell delay = 1.881 ns ( 23.76 % )
        Info: Total interconnect delay = 6.037 ns ( 76.24 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Sun Apr 19 10:47:45 2009
    Info: Elapsed time: 00:00:00