📄 shifter.tan.rpt
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Classic Timing Analyzer report for shifter
Sun Apr 19 10:47:45 2009
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. tpd
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------+----------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.133 ns ; d[7] ; cn$latch ; -- ; s[0] ; 0 ;
; Worst-case tco ; N/A ; None ; 9.809 ns ; cn$latch ; cn ; m ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 18.427 ns ; d[3] ; qb[5] ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -2.675 ns ; d[0] ; cn$latch ; -- ; m ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+----------+----------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C12Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; s[0] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; s[1] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; m ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+----------+----------+
; N/A ; None ; 6.133 ns ; d[7] ; cn$latch ; s[0] ;
; N/A ; None ; 5.799 ns ; d[7] ; cn$latch ; s[1] ;
; N/A ; None ; 5.642 ns ; s[0] ; cn$latch ; s[0] ;
; N/A ; None ; 5.325 ns ; d[0] ; cn$latch ; s[0] ;
; N/A ; None ; 5.308 ns ; s[0] ; cn$latch ; s[1] ;
; N/A ; None ; 4.991 ns ; d[0] ; cn$latch ; s[1] ;
; N/A ; None ; 4.443 ns ; d[7] ; cn$latch ; m ;
; N/A ; None ; 3.952 ns ; s[0] ; cn$latch ; m ;
; N/A ; None ; 3.635 ns ; d[0] ; cn$latch ; m ;
+-------+--------------+------------+------+----------+----------+
+----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+----+------------+
; N/A ; None ; 9.809 ns ; cn$latch ; cn ; m ;
; N/A ; None ; 8.453 ns ; cn$latch ; cn ; s[1] ;
; N/A ; None ; 8.119 ns ; cn$latch ; cn ; s[0] ;
+-------+--------------+------------+----------+----+------------+
+------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+-------+
; N/A ; None ; 18.427 ns ; d[3] ; qb[5] ;
; N/A ; None ; 18.209 ns ; d[3] ; qb[7] ;
; N/A ; None ; 18.109 ns ; d[3] ; qb[4] ;
; N/A ; None ; 17.776 ns ; d[3] ; qb[6] ;
; N/A ; None ; 17.760 ns ; d[3] ; qb[3] ;
; N/A ; None ; 16.293 ns ; d[1] ; qb[5] ;
; N/A ; None ; 16.173 ns ; d[4] ; qb[5] ;
; N/A ; None ; 16.141 ns ; d[1] ; qb[3] ;
; N/A ; None ; 16.075 ns ; d[1] ; qb[7] ;
; N/A ; None ; 16.066 ns ; d[0] ; qb[5] ;
; N/A ; None ; 16.003 ns ; m ; qb[7] ;
; N/A ; None ; 15.977 ns ; d[1] ; qb[4] ;
; N/A ; None ; 15.955 ns ; d[4] ; qb[7] ;
; N/A ; None ; 15.918 ns ; d[0] ; qb[3] ;
; N/A ; None ; 15.861 ns ; d[0] ; qb[1] ;
; N/A ; None ; 15.848 ns ; d[0] ; qb[7] ;
; N/A ; None ; 15.754 ns ; d[0] ; qb[4] ;
; N/A ; None ; 15.642 ns ; d[1] ; qb[6] ;
; N/A ; None ; 15.579 ns ; co ; qb[5] ;
; N/A ; None ; 15.569 ns ; d[2] ; qb[5] ;
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