fsm.vhd

来自「上海交通大学VHDL课程的所有作业代码」· VHDL 代码 · 共 67 行

--10110
ENTITY fsm IS
PORT(
clock, x :  IN BIT; 
z :   	 OUT BIT);
END fsm;
-------------------------------------------------
ARCHITECTURE using_wait OF fsm IS
TYPE state_type IS (s0, s1, s2, s3,s4,s5);
BEGIN
PROCESS
VARIABLE state : state_type := s0;
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');
CASE state IS
WHEN s0 => IF x = '0' THEN
state := s0;
z <= '0';
ELSE
state := s1;
z <= '0';
END IF;

WHEN s1 => IF x = '1' THEN
state := s0;
z <= '0';
ELSE
state := s2;
z <= '0';
END IF;

WHEN s2 => IF x = '0' THEN
state := s0;
z <= '0';
ELSE
state := s3;
z <= '0';
END IF;

WHEN s3 => IF x = '0' THEN
state := s0;
z <= '0';
ELSE
state := s4;
z <= '0';
END IF;

WHEN s4 => IF x = '1' THEN
state := s0;
z <= '0';
ELSE
state := s5;
z <= '1';
end if;

WHEN s5 => IF x = '0' THEN
state := s0;
z <= '0';
ELSE
state := s1;
z <= '0';
END IF;

END CASE;
END PROCESS;
END using_wait;