clk_div.vhd

来自「上海交通大学VHDL课程的所有作业代码」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CLK_DIV IS
		PORT(CLK:IN STD_LOGIC;
					OUT1:BUFFER STD_LOGIC);
		END CLK_DIV;
		
ARCHITECTURE EXAMPLE OF CLK_DIV IS
		SIGNAL COUNT1:INTEGER RANGE 0 TO 33554432;
BEGIN
		PROCESS (CLK)
		VARIABLE COUNT2:INTEGER RANGE 0 TO 33554432;
	BEGIN 
		IF (CLK'EVENT AND CLK='1') THEN
		COUNT1<=COUNT1+1;
		IF(COUNT1=33554431) THEN
			OUT1<=NOT OUT1;
			COUNT1<=0;
		END IF;
	END IF;
END PROCESS;
END EXAMPLE;