digilock.vhd

上海交通大学VHDL课程的所有作业代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DIGILOCK IS
	PORT (	INPUT : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			MODIFY : IN STD_LOGIC;
			--SET : IN STD_LOGIC;
			RESET,CLK : IN STD_LOGIC;
			RED : OUT STD_LOGIC;
			GRE : OUT STD_LOGIC;
			MODI_L : OUT STD_LOGIC);
END DIGILOCK;

ARCHITECTURE ABC OF DIGILOCK IS 
	TYPE STATE IS (STATE0,STATE1);
	SIGNAL C_STATE : STATE;
	SIGNAL CODE : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	--PROCESS (RESET)
	--BEGIN
		
	--END PROCESS;
	
	PROCESS (CLK,RESET)
	BEGIN    
		IF(RESET = '0') THEN 
			C_STATE <= STATE0;
			CODE <= "00000001";
			GRE <= '0';
			RED <= '1';
			MODI_L <= '0';
		ELSE
		CASE C_STATE IS
		WHEN STATE0 =>
			RED <= '1';
			GRE <= '0';
			MODI_L <= '0';
			IF(INPUT = CODE) THEN 
				C_STATE <= STATE1;
			END IF;
			
		WHEN STATE1 =>
			RED <= '0';
			GRE <= '1';
			MODI_L <= MODIFY;
			IF(MODIFY = '1') THEN
				CODE <= INPUT;
			ELSIF(INPUT = CODE) THEN
			ELSE
				C_STATE <= STATE0;
			END IF;
			
		END CASE;
		END IF;
	END PROCESS;
END ABC;