maj2.vhd

上海交通大学VHDL课程的所有作业代码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY maj2 IS
PORT (a, b, c :  IN BIT; 
m :    OUT BIT);
END maj2;
ARCHITECTURE concurrent OF maj2 IS
BEGIN
WITH a&b&c SELECT
m <= '1' WHEN "110"|"101"|"011"|"111",
'0' WHEN OTHERS;
END concurrent;