maj4.vhd

上海交通大学VHDL课程的所有作业代码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY maj4 IS
PORT (a, b, c, d,e :  IN BIT; 
m :    OUT BIT);
END maj4;
ARCHITECTURE concurrent OF maj4 IS
BEGIN
WITH a&b&c&d&e SELECT
m <= '1' WHEN "00111"|"01110"|"01101"|"01011"|"10110"|"10101"|"10011"|"11001"|"11010"|"11100"|"01111"|"10111"|"11011"|"11101"|"11110"|"11111",
'0' WHEN OTHERS;
END concurrent;