gcode.vhd

上海交通大学VHDL课程的所有作业代码

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
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ENTITY GCODE IS
	PORT (clk,sw0,sw1,sw2,sw3,sw17: IN STD_LOGIC;
			ledr0,ledr1,ledr2,ledr3,ledr17: BUFFER STD_LOGIC);
	END GCODE;
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ARCHITECTURE example OF GCODE IS
BEGIN
	PROCESS (clk)
  BEGIN
		if(sw17='1') then
			ledr3<=sw3;
			ledr2<=ledr3 xor sw2;
			ledr1<=ledr2 xor sw1;
			ledr0<=ledr1 xor sw0;
		end if;
		if(sw17='0') then
			ledr3<=sw3;
			ledr2<=sw3 xor sw2;
			ledr1<=sw2 xor sw1;
			ledr0<=sw1 xor sw0;	
		end if;		
	--ledr17<=sw17;	
end process;
ledr17<=sw17;
end example;