bicounter.vhd

上海交通大学VHDL课程的所有作业代码

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
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ENTITY BICOUNTER IS
	PORT (clk,sw17,reset: IN STD_LOGIC;
			ledr0,ledr1,ledr2,ledr3,ledr17: BUFFER STD_LOGIC);
	END BICOUNTER;
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ARCHITECTURE example OF BICOUNTER IS
	SIGNAL carry1: STD_LOGIC;
	SIGNAL count2: std_logic_vector(0 to 3);
BEGIN
	PROCESS (clk)
	VARIABLE count1:INTEGER RANGE 0 TO 33554432;
  BEGIN
	IF (clk'EVENT AND clk = '1' ) THEN
		count1:=count1+1;
		if (count1=33554432) then
			carry1<=not carry1;
			count1:=0;
		end if;
	end if;
	if(carry1'EVENT AND carry1 = '1') then
		if(sw17='1') then
			if(reset='0') then
				count2<="0000";
			else
				count2<=count2+"1";
			end if;	
		end if;
		
		if(sw17='0') then
			if(reset='0') then
				count2<="1111";
			else
				count2<=count2-1;
			end if;	
		end if;		
	end if;
	ledr3<=not count2(0);
	ledr2<=not count2(1);
	ledr1<=not count2(2);
	ledr0<=not count2(3);
	--ledr17<=sw17;	
end process;
ledr17<=sw17;
end example;