test_comblock.vhd

海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述

library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;

architecture v1 of testbench is

	-- Inputs
	signal clock, clear : std_logic;
	signal SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7 : std_logic;
	--signal switches : std_logic_vector(7 downto 0);

	-- Outputs
   signal alarm, locked : std_logic;
	signal SA, SB, SC, SD, SE, SF, SG : std_logic;

	--procedure to delay by a number of clock edges
	procedure clock_ticks(signal clock : in std_logic; num : in positive) is
	begin
		for i in 1 to num loop
			wait until falling_edge(clock);
		end loop;			
	end procedure clock_ticks;

begin

	-- Instantiate the UUT
	--UUT : entity work.comblock(Structure) --use this for timing
   	UUT : entity work.comblock(v1) --use this for functional
				port map(
					clock => clock, 
					clear => clear, 
					SW0 => SW0, SW1 => SW1, SW2 => SW2, SW3 => SW3, 
					SW4 => SW4, SW5 => SW5, SW6 => SW6, SW7 => SW7, 
					alarm => alarm, 
					locked => locked,
					SA => SA,
					SB => SB, 
					SC => SC, 
					SD => SD, 
					SE => SE, 
					SF => SF, 
					SG => SG);

	--generate a 10kHz clock
	clock_loop : process
	begin
		clock <= '0';
		loop 
			wait for 50 us;
			clock <= not clock;
		end loop;
	end process;

	stim : process
	begin
		--reset the fsm and set all switches high
		clear <= '1'; 
		SW0 <= '1'; 
		SW1 <= '1'; 
		SW2 <= '1'; 
		SW3 <= '1'; 
		SW4 <= '1'; 
		SW5 <= '1'; 
		SW6 <= '1'; 
		SW7 <= '1';
		--switches <= "11111111";
		
		clock_ticks(clock, 3);	
		clear <= '0';
	
		--apply correct code
		clock_ticks(clock, 5);
		SW0 <= '0';	
		clock_ticks(clock, 3);
		SW0 <= '1';
		
		clock_ticks(clock, 5);
		SW1 <= '0';	
		clock_ticks(clock, 3);
		SW1 <= '1';
		
		clock_ticks(clock, 5);
		SW2 <= '0';
		clock_ticks(clock, 3);
		SW2 <= '1';
		
		clock_ticks(clock, 5);
		SW3 <= '0';
		clock_ticks(clock, 3);
		SW3 <= '1';	
		
		--wait for auto-lock timeout
		clock_ticks(clock, 400);
	
		--reset the combination lock
		clear <= '1';
		clock_ticks(clock, 4);
		clear <= '0';
	
		--apply incorrect code
		clock_ticks(clock, 5); 
		SW0 <= '0';
		clock_ticks(clock, 3);
		SW0 <= '1';
		
		clock_ticks(clock, 5);
		SW5 <= '0';
		clock_ticks(clock, 3);
		SW5 <= '1';
		
		clock_ticks(clock, 5);
		SW2 <= '0';
		clock_ticks(clock, 3);
		SW2 <= '1';
		
		clock_ticks(clock, 5);
		SW3 <= '0';
		clock_ticks(clock, 3);
		SW3 <= '1';
		
		clock_ticks(clock, 5);
		clear <= '0';
		
		clock_ticks(clock, 10);
		
		--stop the simulator
		assert false report "simulation ended" severity failure;
	end process;

end architecture v1;