comblock.vhd

海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述

library ieee;
use ieee.std_logic_1164.all;
entity comblock is
	port(clock, clear : in std_logic; 
			SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7 : in std_logic; 
			alarm, locked : buffer std_logic;
			SA, SB, SC, SD, SE, SF, SG : out std_logic);
end comblock;

architecture v1 of comblock is

	signal mux_out, anysw, codesw, allsw : std_logic;
	signal selsw : std_logic_vector(1 downto 0);
	signal SEG : std_logic_vector(6 downto 0); --display value	
	signal start_timer, timed_out : std_logic; --timer signals
	
begin 			
	
	--switch multiplexer
	mux_out <= SW0 when selsw = "00" else
					SW1 when selsw = "01" else
					SW2 when selsw = "10" else
					SW3 when selsw = "11" else
					'0';			

	--and all the switches
	allsw <= SW0 and SW1 and SW2 and SW3 and 
				SW4 and SW5 and SW6 and SW7;
	
	det1 : entity work.edgedet(v1)
			port map(edge_in => mux_out, 
				detected => codesw, 
				clock => clock,
				reset => clear);
				
	det2 : entity work.edgedet(v1)
			port map(edge_in => allsw, 
				detected => anysw, 
				clock => clock,
				reset => clear);

	controller : entity work.lockfsm(v1)
			port map(clock => clock, 
					reset => clear, 
					codesw => codesw, 
					anysw => anysw, 
					selsw => selsw, 
					locked => locked, 
					alarm => alarm,
					start_timer => start_timer,
					timed_out => timed_out);

	t1 : entity work.Timer(Behavioral)
				generic map(MAX => 300)	 --set to required time delay
   			Port map(clk => clock,	
			   		reset => clear,
           			start => start_timer,	
           			timeout => timed_out); 

	--decode 'alarm' and 'locked', SEG = a,b,c,d,e,f,g
	--changed to active-high LEDs 15-4-09
	SEG <= "1110111" when alarm = '0' else --A
			"0111110" when locked = '0' else  --U
			"0001110";                        --L

	--connect segment code to segments
	SA <= SEG(6);
	SB <= SEG(5);
	SC <= SEG(4);
	SD <= SEG(3);
	SE <= SEG(2);
	SF <= SEG(1);
	SG <= SEG(0);

end architecture v1;