lockfsm.vhd

海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述

library ieee;
use ieee.std_logic_1164.all;
entity lockfsm is
	port(
		clock, 
		reset, 
		codesw, 
		anysw : in std_logic;
		selsw : out std_logic_vector(1 downto 0); 
		locked, 
		alarm : buffer std_logic;
		start_timer : out std_logic;
		timed_out : in std_logic
		);
end lockfsm;

architecture v1 of lockfsm is
	
	type state_type is (s0, s1, s2, s3, wrong, unlock);
	signal lockstate : state_type;

begin

	ns_proc : process(reset, clock)
	begin
		if reset = '1' then
			lockstate <= s0;
		elsif rising_edge(clock) then
			case lockstate is
				when s0 => 
					if (anysw = '1') and (codesw = '1') then
						lockstate <= s1;
				 	elsif (anysw = '1') then 
						lockstate <= wrong;	
				 	else
						lockstate <= s0;
					end if;			
				when s1 => 
					if (anysw = '1') and (codesw = '1') then
						lockstate <= s2;
				 	elsif (anysw = '1') then 
						lockstate <= wrong;	
					else
						lockstate <= s1;	
					end if;		
				when s2 => 
					if (anysw = '1') and (codesw = '1') then
						lockstate <= s3;
				 	elsif (anysw = '1') then 
						lockstate <= wrong;	
				 	else
						lockstate <= s2;			
					end if;
				when s3 => 
					if (anysw = '1') and (codesw = '1') then
						lockstate <= unlock;
				 	elsif (anysw = '1') then 
						lockstate <= wrong;	
				 	else
						lockstate <= s3;			
					end if;
				when wrong => 
					lockstate <= wrong;
				when unlock =>
					if timed_out = '1' then
						lockstate <= s0;
					else
						lockstate <= unlock;
					end if;
				when others => lockstate <= s0;
			end case;
		end if;
	end process;

	--assign select switch
	with lockstate select
		selsw <= "01" when s1,
					"10" when s2,
					"11" when s3,
					"00" when others;

	--assign outputs (leds are active-low)
	locked <= '0' when lockstate = unlock else '1';
	alarm <= '0' when lockstate = wrong else '1';
	
	--timer control
	start_timer <= '1' when lockstate = unlock else '0';

end v1;