par_to_ser.sim.rpt

一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据

; |par_to_ser|ds[2] ; |par_to_ser|ds[2]~corein ; dataout          ;
; |par_to_ser|ds[1] ; |par_to_ser|ds[1]~corein ; dataout          ;
; |par_to_ser|ds[0] ; |par_to_ser|ds[0]~corein ; dataout          ;
+-------------------+--------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                              ;
+----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                              ; Output Port Name                                                                          ; Output Port Type ;
+----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+
; |par_to_ser|dp~reg0                                                                    ; |par_to_ser|dp~reg0                                                                       ; data_out0        ;
; |par_to_ser|dst[11]                                                                    ; |par_to_ser|dst[11]                                                                       ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]                 ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]                 ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ; cout             ;
; |par_to_ser|LessThan0~30                                                               ; |par_to_ser|LessThan0~30                                                                  ; data_out0        ;
; |par_to_ser|dst[10]                                                                    ; |par_to_ser|dst[10]                                                                       ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1    ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; cout             ;
; |par_to_ser|dst[9]                                                                     ; |par_to_ser|dst[9]                                                                        ; data_out0        ;
; |par_to_ser|dst[8]                                                                     ; |par_to_ser|dst[8]                                                                        ; data_out0        ;
; |par_to_ser|dst[7]                                                                     ; |par_to_ser|dst[7]                                                                        ; data_out0        ;
; |par_to_ser|dst[6]                                                                     ; |par_to_ser|dst[6]                                                                        ; data_out0        ;
; |par_to_ser|dst[5]                                                                     ; |par_to_ser|dst[5]                                                                        ; data_out0        ;
; |par_to_ser|dst[4]                                                                     ; |par_to_ser|dst[4]                                                                        ; data_out0        ;
; |par_to_ser|dst[3]                                                                     ; |par_to_ser|dst[3]                                                                        ; data_out0        ;
; |par_to_ser|dst[2]                                                                     ; |par_to_ser|dst[2]                                                                        ; data_out0        ;
; |par_to_ser|dst[1]                                                                     ; |par_to_ser|dst[1]                                                                        ; data_out0        ;
; |par_to_ser|dst[0]                                                                     ; |par_to_ser|dst[0]                                                                        ; data_out0        ;
; |par_to_ser|dp~1                                                                       ; |par_to_ser|dp~1                                                                          ; data_out0        ;
; |par_to_ser|ds[11]                                                                     ; |par_to_ser|ds[11]~corein                                                                 ; dataout          ;
; |par_to_ser|ds[10]                                                                     ; |par_to_ser|ds[10]~corein                                                                 ; dataout          ;
; |par_to_ser|ds[9]                                                                      ; |par_to_ser|ds[9]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[8]                                                                      ; |par_to_ser|ds[8]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[7]                                                                      ; |par_to_ser|ds[7]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[6]                                                                      ; |par_to_ser|ds[6]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[5]                                                                      ; |par_to_ser|ds[5]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[4]                                                                      ; |par_to_ser|ds[4]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[3]                                                                      ; |par_to_ser|ds[3]~corein                                                                  ; dataout          ;
; |par_to_ser|dp                                                                         ; |par_to_ser|dp                                                                            ; padio            ;
+----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                                              ;
+----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                              ; Output Port Name                                                                          ; Output Port Type ;
+----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+
; |par_to_ser|dp~reg0                                                                    ; |par_to_ser|dp~reg0                                                                       ; data_out0        ;
; |par_to_ser|dst[11]                                                                    ; |par_to_ser|dst[11]                                                                       ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]                 ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]                 ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ; cout             ;
; |par_to_ser|LessThan0~30                                                               ; |par_to_ser|LessThan0~30                                                                  ; data_out0        ;
; |par_to_ser|dst[10]                                                                    ; |par_to_ser|dst[10]                                                                       ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1 ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1    ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; cout             ;
; |par_to_ser|dst[9]                                                                     ; |par_to_ser|dst[9]                                                                        ; data_out0        ;
; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]   ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ; cout             ;
; |par_to_ser|dst[8]                                                                     ; |par_to_ser|dst[8]                                                                        ; data_out0        ;
; |par_to_ser|dst[7]                                                                     ; |par_to_ser|dst[7]                                                                        ; data_out0        ;
; |par_to_ser|dst[6]                                                                     ; |par_to_ser|dst[6]                                                                        ; data_out0        ;
; |par_to_ser|dst[5]                                                                     ; |par_to_ser|dst[5]                                                                        ; data_out0        ;
; |par_to_ser|dst[4]                                                                     ; |par_to_ser|dst[4]                                                                        ; data_out0        ;
; |par_to_ser|dst[3]                                                                     ; |par_to_ser|dst[3]                                                                        ; data_out0        ;
; |par_to_ser|dst[2]                                                                     ; |par_to_ser|dst[2]                                                                        ; data_out0        ;
; |par_to_ser|dst[1]                                                                     ; |par_to_ser|dst[1]                                                                        ; data_out0        ;
; |par_to_ser|dst[0]                                                                     ; |par_to_ser|dst[0]                                                                        ; data_out0        ;
; |par_to_ser|dp~1                                                                       ; |par_to_ser|dp~1                                                                          ; data_out0        ;
; |par_to_ser|ds[11]                                                                     ; |par_to_ser|ds[11]~corein                                                                 ; dataout          ;
; |par_to_ser|ds[10]                                                                     ; |par_to_ser|ds[10]~corein                                                                 ; dataout          ;
; |par_to_ser|ds[9]                                                                      ; |par_to_ser|ds[9]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[8]                                                                      ; |par_to_ser|ds[8]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[7]                                                                      ; |par_to_ser|ds[7]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[6]                                                                      ; |par_to_ser|ds[6]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[5]                                                                      ; |par_to_ser|ds[5]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[4]                                                                      ; |par_to_ser|ds[4]~corein                                                                  ; dataout          ;
; |par_to_ser|ds[3]                                                                      ; |par_to_ser|ds[3]~corein                                                                  ; dataout          ;
; |par_to_ser|dp                                                                         ; |par_to_ser|dp                                                                            ; padio            ;
+----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Apr 25 10:18:11 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off par_to_ser -c par_to_ser
Info: Using vector source file "C:/Documents and Settings/Administrator/桌面/毕设进行/并转串/par_to_ser.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      13.89 %
Info: Number of transitions in simulation is 215
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 97 megabytes of memory during processing
    Info: Processing ended: Sat Apr 25 10:18:12 2009
    Info: Elapsed time: 00:00:01