par_to_ser.map.rpt

一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据

; alt_counter_f10ke.tdf            ; yes             ; Megafunction           ; c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf        ;
; flex10ke_lcell.inc               ; yes             ; Megafunction           ; c:/altera/72/quartus/libraries/megafunctions/flex10ke_lcell.inc           ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 20      ;
; Total combinational functions     ; 19      ;
;     -- Total 4-input functions    ; 0       ;
;     -- Total 3-input functions    ; 13      ;
;     -- Total 2-input functions    ; 5       ;
;     -- Total 1-input functions    ; 1       ;
;     -- Total 0-input functions    ; 0       ;
; Total registers                   ; 17      ;
; Total logic cells in carry chains ; 4       ;
; I/O pins                          ; 15      ;
; Maximum fan-out node              ; rst     ;
; Maximum fan-out                   ; 18      ;
; Total fan-out                     ; 86      ;
; Average fan-out                   ; 2.46    ;
+-----------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                 ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                  ; Library Name ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------+--------------+
; |par_to_ser                            ; 20 (15)     ; 17           ; 0           ; 15   ; 3 (2)        ; 1 (1)             ; 16 (12)          ; 4 (0)           ; 0 (0)      ; |par_to_ser                                                          ; work         ;
;    |lpm_counter:counter_rtl_0|         ; 5 (0)       ; 4            ; 0           ; 0    ; 1 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; 0 (0)      ; |par_to_ser|lpm_counter:counter_rtl_0                                ; work         ;
;       |alt_counter_f10ke:wysi_counter| ; 5 (5)       ; 4            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; 0 (0)      ; |par_to_ser|lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter ; work         ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 17    ;
; Number of registers using Synchronous Clear  ; 4     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 1     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 17    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Source assignments for lpm_counter:counter_rtl_0 ;
+---------------------------+-------+------+-------+
; Assignment                ; Value ; From ; To    ;
+---------------------------+-------+------+-------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -     ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -     ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -     ;
+---------------------------+-------+------+-------+


+----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:counter_rtl_0 ;
+------------------------+-------------------+-------------------------------+
; Parameter Name         ; Value             ; Type                          ;
+------------------------+-------------------+-------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                    ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                  ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                  ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                ;
; LPM_WIDTH              ; 4                 ; Untyped                       ;
; LPM_DIRECTION          ; UP                ; Untyped                       ;
; LPM_MODULUS            ; 0                 ; Untyped                       ;
; LPM_AVALUE             ; UNUSED            ; Untyped                       ;
; LPM_SVALUE             ; UNUSED            ; Untyped                       ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                       ;
; DEVICE_FAMILY          ; FLEX10K           ; Untyped                       ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                       ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH            ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK            ;
; CARRY_CNT_EN           ; SMART             ; Untyped                       ;
; LABWIDE_SCLR           ; ON                ; Untyped                       ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                       ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                       ;
+------------------------+-------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Apr 25 10:17:52 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off par_to_ser -c par_to_ser
Info: Found 1 design units, including 1 entities, in source file par_to_ser.v
    Info: Found entity 1: par_to_ser
Info: Elaborating entity "par_to_ser" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at par_to_ser.v(23): truncated value with size 32 to match size of target (4)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter[0]~4"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/72/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "lpm_counter:counter_rtl_0"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "lpm_counter:counter_rtl_0"
Info: Instantiated megafunction "lpm_counter:counter_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 1 output pins
    Info: Implemented 20 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 137 megabytes of memory during processing
    Info: Processing ended: Sat Apr 25 10:17:55 2009
    Info: Elapsed time: 00:00:03