par_to_ser.tan.rpt

一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据

; N/A           ; None        ; 1.100 ns  ; rst    ; dst[3]                                                        ; clk      ;
; N/A           ; None        ; 1.100 ns  ; rst    ; dst[2]                                                        ; clk      ;
; N/A           ; None        ; 0.800 ns  ; ds[8]  ; dst[8]                                                        ; clk      ;
; N/A           ; None        ; 0.800 ns  ; ds[9]  ; dst[9]                                                        ; clk      ;
; N/A           ; None        ; 0.800 ns  ; rst    ; dst[11]                                                       ; clk      ;
; N/A           ; None        ; 0.800 ns  ; rst    ; dst[10]                                                       ; clk      ;
; N/A           ; None        ; 0.800 ns  ; rst    ; lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; rst    ; lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; rst    ; lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; rst    ; lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; rst    ; dst[1]                                                        ; clk      ;
; N/A           ; None        ; 0.800 ns  ; rst    ; dst[0]                                                        ; clk      ;
; N/A           ; None        ; 0.700 ns  ; ds[10] ; dst[10]                                                       ; clk      ;
; N/A           ; None        ; 0.700 ns  ; ds[11] ; dst[11]                                                       ; clk      ;
; N/A           ; None        ; -0.600 ns ; ds[0]  ; dst[0]                                                        ; clk      ;
; N/A           ; None        ; -1.000 ns ; ds[1]  ; dst[1]                                                        ; clk      ;
; N/A           ; None        ; -1.200 ns ; ds[2]  ; dst[2]                                                        ; clk      ;
; N/A           ; None        ; -1.200 ns ; ds[3]  ; dst[3]                                                        ; clk      ;
; N/A           ; None        ; -1.200 ns ; ds[4]  ; dst[4]                                                        ; clk      ;
; N/A           ; None        ; -1.200 ns ; ds[7]  ; dst[7]                                                        ; clk      ;
; N/A           ; None        ; -2.400 ns ; ds[5]  ; dst[5]                                                        ; clk      ;
; N/A           ; None        ; -2.400 ns ; ds[6]  ; dst[6]                                                        ; clk      ;
+---------------+-------------+-----------+--------+---------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Apr 25 10:18:05 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off par_to_ser -c par_to_ser
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 81.3 MHz between source register "lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" and destination register "dp~reg0" (period= 12.3 ns)
    Info: + Longest register to register delay is 8.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_B14; Fanout = 4; REG Node = 'lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_B14; Fanout = 12; COMB Node = 'LessThan0~30'
        Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 6.900 ns; Loc. = LC3_B13; Fanout = 1; COMB Node = 'dp~1'
        Info: 4: + IC(0.600 ns) + CELL(1.200 ns) = 8.700 ns; Loc. = LC5_B13; Fanout = 1; REG Node = 'dp~reg0'
        Info: Total cell delay = 5.300 ns ( 60.92 % )
        Info: Total interconnect delay = 3.400 ns ( 39.08 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_B13; Fanout = 1; REG Node = 'dp~reg0'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock "clk" to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_B14; Fanout = 4; REG Node = 'lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" (data pin = "rst", clock pin = "clk") is 6.700 ns
    Info: + Longest pin to register delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_126; Fanout = 23; PIN Node = 'rst'
        Info: 2: + IC(2.100 ns) + CELL(2.300 ns) = 7.200 ns; Loc. = LC3_B14; Fanout = 4; COMB Node = 'lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~1'
        Info: 3: + IC(0.600 ns) + CELL(1.700 ns) = 9.500 ns; Loc. = LC7_B14; Fanout = 4; REG Node = 'lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 6.800 ns ( 71.58 % )
        Info: Total interconnect delay = 2.700 ns ( 28.42 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "clk" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_B14; Fanout = 4; REG Node = 'lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "clk" to destination pin "dp" through register "dp~reg0" is 13.200 ns
    Info: + Longest clock path from clock "clk" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_B13; Fanout = 1; REG Node = 'dp~reg0'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 6.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B13; Fanout = 1; REG Node = 'dp~reg0'
        Info: 2: + IC(1.700 ns) + CELL(5.100 ns) = 6.800 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'dp'
        Info: Total cell delay = 5.100 ns ( 75.00 % )
        Info: Total interconnect delay = 1.700 ns ( 25.00 % )
Info: th for register "dst[9]" (data pin = "rst", clock pin = "clk") is 1.100 ns
    Info: + Longest clock path from clock "clk" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_B21; Fanout = 1; REG Node = 'dst[9]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 5.800 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_126; Fanout = 23; PIN Node = 'rst'
        Info: 2: + IC(1.800 ns) + CELL(1.200 ns) = 5.800 ns; Loc. = LC1_B21; Fanout = 1; REG Node = 'dst[9]'
        Info: Total cell delay = 4.000 ns ( 68.97 % )
        Info: Total interconnect delay = 1.800 ns ( 31.03 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Sat Apr 25 10:18:06 2009
    Info: Elapsed time: 00:00:01