second.vhd

来自「一个时钟计数器」· VHDL 代码 · 共 42 行

-------------------------------------------------
--实体名：second
--功  能：对输入时钟进行50000000分频，得到1Hz信号
--接  口：clk -时钟输入
--        qout-秒输出信号
--作  者：Haibing Li
--日  期：2006-11
-------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity second is
port
(clk:in std_logic;
 qout:out std_logic
);
end second;

architecture behave of second is
constant counter_len:integer:=49999999;
begin
  process(clk)
  variable cnt:integer range 0 to counter_len;
  begin
    if clk'event and clk='1' then
       if cnt=counter_len then
          cnt:=0;
       else
          cnt:=cnt+1;
       end if;

       case cnt is
         when 0 to counter_len/2=>qout<='0';
         when others            =>qout<='1';
       end case;
    end if;
  end process;

end behave;