add.vhd

来自「一位全加器源码实现了MAX及其一系列器件实现全加的功能」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY add IS 
PORT (x,y,Cin:IN std_logic;
            Sum,Cout:OUT std_logic);
END add;
ARCHITECTURE a_adder OF add IS
SIGNAL S:std_logic;
BEGIN
S<=x XOR y;
Sum<=S XOR Cin;
Cout<=(S AND Cin) OR(x AND y);
END a_adder;