mcu8951.tan.summary

Alera 的8051 IP core的示例文件5个

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -0.049 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[7]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.385 ns
From           : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[4]
To             : POE[1]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 3.056 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 12.342 ns
From           : MT
To             : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|Q
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case Minimum Pulse Width Requirement (Low)
Slack          : -0.567 ns
Required Time  : 3.067 ns
Actual Time    : 2.500 ns
From           : pll50:inst17|altpll:altpll_component|_clk0
To             : rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_kod1:auto_generated|altsyncram_22d2:altsyncram1|ram_block3a0~porta_address_reg0
From Clock     : --
To Clock       : --
Failed Paths   : 121

Type           : Worst-case Minimum Pulse Width Requirement (High)
Slack          : -0.567 ns
Required Time  : 3.067 ns
Actual Time    : 2.500 ns
From           : pll50:inst17|altpll:altpll_component|_clk0
To             : rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_kod1:auto_generated|altsyncram_22d2:altsyncram1|ram_block3a0~porta_address_reg0
From Clock     : --
To Clock       : --
Failed Paths   : 121

Type           : Clock Setup: 'pll50:inst17|altpll:altpll_component|_clk0'
Slack          : -15.530 ns
Required Time  : 200.00 MHz ( period = 5.000 ns )
Actual Time    : 48.71 MHz ( period = 20.530 ns )
From           : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3]
To             : CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[4]
From Clock     : pll50:inst17|altpll:altpll_component|_clk0
To Clock       : pll50:inst17|altpll:altpll_component|_clk0
Failed Paths   : 8940

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 83.68 MHz ( period = 11.950 ns )
From           : ram256:inst6|altsyncram:altsyncram_component|altsyncram_vbg1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'pll50:inst17|altpll:altpll_component|_clk0'
Slack          : -7.266 ns
Required Time  : 200.00 MHz ( period = 5.000 ns )
Actual Time    : N/A
From           : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|STX.st0
To             : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|STX.st0
From Clock     : pll50:inst17|altpll:altpll_component|_clk0
To Clock       : pll50:inst17|altpll:altpll_component|_clk0
Failed Paths   : 160

Type           : Other violations (see messages)
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 9343

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