mcu8951.fit.rpt

Alera 的8051 IP core的示例文件5个

; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/张古月/桌面/KX_7C_TUTRL/TUT1_BASIC1_7C5TP/MCU8951.pin.


+--------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                    ;
+---------------------------------------------+----------------------------------------------------+
; Resource                                    ; Usage                                              ;
+---------------------------------------------+----------------------------------------------------+
; Total logic elements                        ; 1,848 / 4,608 ( 40 % )                             ;
;     -- Combinational with no register       ; 1164                                               ;
;     -- Register only                        ; 46                                                 ;
;     -- Combinational with a register        ; 638                                                ;
;                                             ;                                                    ;
; Logic element usage by number of LUT inputs ;                                                    ;
;     -- 4 input functions                    ; 1162                                               ;
;     -- 3 input functions                    ; 408                                                ;
;     -- <=2 input functions                  ; 232                                                ;
;     -- Register only                        ; 46                                                 ;
;                                             ;                                                    ;
; Logic elements by mode                      ;                                                    ;
;     -- normal mode                          ; 1729                                               ;
;     -- arithmetic mode                      ; 73                                                 ;
;                                             ;                                                    ;
; Total registers*                            ; 684 / 4,851 ( 14 % )                               ;
;     -- Dedicated logic registers            ; 684 / 4,608 ( 15 % )                               ;
;     -- I/O registers                        ; 0 / 243 ( 0 % )                                    ;
;                                             ;                                                    ;
; Total LABs:  partially or completely used   ; 138 / 288 ( 48 % )                                 ;
; User inserted logic elements                ; 0                                                  ;
; Virtual pins                                ; 0                                                  ;
; I/O pins                                    ; 17 / 89 ( 19 % )                                   ;
;     -- Clock pins                           ; 2 / 4 ( 50 % )                                     ;
; Global signals                              ; 8                                                  ;
; M4Ks                                        ; 9 / 26 ( 35 % )                                    ;
; Total memory bits                           ; 34,816 / 119,808 ( 29 % )                          ;
; Total RAM block bits                        ; 41,472 / 119,808 ( 35 % )                          ;
; Embedded Multiplier 9-bit elements          ; 0 / 26 ( 0 % )                                     ;
; PLLs                                        ; 1 / 2 ( 50 % )                                     ;
; Global clocks                               ; 8 / 8 ( 100 % )                                    ;
; Average interconnect usage                  ; 10%                                                ;
; Peak interconnect usage                     ; 16%                                                ;
; Maximum fan-out node                        ; pll50:inst17|altpll:altpll_component|_clk0~clkctrl ;
; Maximum fan-out                             ; 456                                                ;
; Highest non-global fan-out signal           ; CPU8051V1:inst|MCU80512:inst3|CLEAR                ;
; Highest non-global fan-out                  ; 166                                                ;
; Total fan-out                               ; 8774                                               ;
; Average fan-out                             ; 3.41                                               ;
+---------------------------------------------+----------------------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                   ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; CLK    ; 17    ; 1        ; 0            ; 6            ; 0           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; K2_P30 ; 58    ; 4        ; 12           ; 0            ; 0           ; 0                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; MT     ; 21    ; 1        ; 0            ; 6            ; 2           ; 4                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; NO     ; 22    ; 1        ; 0            ; 6            ; 3           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;