mcu8951.tan.rpt

Alera 的8051 IP core的示例文件5个

; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll50:inst17|altpll:altpll_component|_clk0 ;                    ; PLL output ; 200.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK      ; 10                    ; 1                   ; -2.243 ns ;              ;
; CLK                                        ;                    ; User Pin   ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP               ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll50:inst17|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                       ; To                                                           ; From Clock                                 ; To Clock                                   ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+-----------------------------+---------------------------+-------------------------+
; -15.530 ns                              ; 48.71 MHz ( period = 20.530 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[4]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 6.718 ns                ;
; -15.299 ns                              ; 49.26 MHz ( period = 20.299 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[6]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 6.487 ns                ;
; -15.280 ns                              ; 49.31 MHz ( period = 20.280 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[4]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 6.468 ns                ;
; -15.111 ns                              ; 49.72 MHz ( period = 20.111 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[4]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 6.299 ns                ;
; -15.049 ns                              ; 49.88 MHz ( period = 20.049 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[6]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 6.237 ns                ;
; -15.038 ns                              ; 49.91 MHz ( period = 20.038 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[7]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 6.226 ns                ;
; -15.008 ns                              ; 49.98 MHz ( period = 20.008 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[5]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 6.196 ns                ;
; -14.880 ns                              ; 50.30 MHz ( period = 19.880 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[6]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 6.068 ns                ;
; -14.867 ns                              ; 50.33 MHz ( period = 19.867 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[1]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.814 ns                 ; 6.053 ns                ;
; -14.799 ns                              ; 50.51 MHz ( period = 19.799 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[2]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.819 ns                 ; 5.980 ns                ;
; -14.788 ns                              ; 50.54 MHz ( period = 19.788 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[7]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 5.976 ns                ;
; -14.758 ns                              ; 50.61 MHz ( period = 19.758 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[5]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 5.946 ns                ;
; -14.745 ns                              ; 50.65 MHz ( period = 19.745 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|ACLDAT[7]          ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.814 ns                 ; 5.931 ns                ;
; -14.636 ns                              ; 50.93 MHz ( period = 19.636 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[0]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.819 ns                 ; 5.817 ns                ;
; -14.619 ns                              ; 50.97 MHz ( period = 19.619 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[7]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 5.807 ns                ;
; -14.617 ns                              ; 50.98 MHz ( period = 19.617 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[1]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.814 ns                 ; 5.803 ns                ;
; -14.616 ns                              ; 50.98 MHz ( period = 19.616 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s025bo:U14|OPC[2]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.820 ns                 ; 5.796 ns                ;
; -14.589 ns                              ; 51.05 MHz ( period = 19.589 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[5]        ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.812 ns                 ; 5.777 ns                ;
; -14.549 ns                              ; 51.15 MHz ( period = 19.549 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[2]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.819 ns                 ; 5.730 ns                ;
; -14.495 ns                              ; 51.30 MHz ( period = 19.495 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|ACLDAT[7]          ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.814 ns                 ; 5.681 ns                ;
; -14.491 ns                              ; 51.31 MHz ( period = 19.491 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[3]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.824 ns                 ; 5.667 ns                ;
; -14.448 ns                              ; 51.42 MHz ( period = 19.448 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[1]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.814 ns                 ; 5.634 ns                ;
; -14.436 ns                              ; 51.45 MHz ( period = 19.436 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|ACLDAT[4]          ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.814 ns                 ; 5.622 ns                ;
; -14.386 ns                              ; 51.58 MHz ( period = 19.386 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[0]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.819 ns                 ; 5.567 ns                ;
; -14.380 ns                              ; 51.60 MHz ( period = 19.380 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[2]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.819 ns                 ; 5.561 ns                ;
; -14.366 ns                              ; 51.64 MHz ( period = 19.366 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s025bo:U14|OPC[2]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.820 ns                 ; 5.546 ns                ;
; -14.330 ns                              ; 51.73 MHz ( period = 19.330 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s025bo:U14|OPC[1]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.819 ns                 ; 5.511 ns                ;
; -14.326 ns                              ; 51.74 MHz ( period = 19.326 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|ACLDAT[7]          ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.814 ns                 ; 5.512 ns                ;
; -14.290 ns                              ; 51.84 MHz ( period = 19.290 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s025bo:U14|OPC[0]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.820 ns                 ; 5.470 ns                ;
; -14.241 ns                              ; 51.97 MHz ( period = 19.241 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] ; CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA[3]            ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.824 ns                 ; 5.417 ns                ;
; -14.234 ns                              ; 51.99 MHz ( period = 19.234 ns )                    ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s010bo:U8|L_PROGRAM_COUNT[7] ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 5.000 ns                    ; -8.804 ns                 ; 5.430 ns                ;