📄 mcu8951.tan.rpt
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+-----------------------------------------------------------+------------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+-----------------------------------------------------------+------------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Worst-case tsu ; N/A ; None ; -0.049 ns ; altera_internal_jtag ; sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[7] ; -- ; altera_internal_jtag~TCKUTAP ; 0 ;
; Worst-case tco ; N/A ; None ; 16.385 ns ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; POE[1] ; CLK ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 3.056 ns ; altera_internal_jtag~TDO ; altera_reserved_tdo ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 12.342 ns ; MT ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|Q ; -- ; CLK ; 0 ;
; Worst-case Minimum Pulse Width Requirement (Low) ; -0.567 ns ; 3.067 ns ; 2.500 ns ; pll50:inst17|altpll:altpll_component|_clk0 ; rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_kod1:auto_generated|altsyncram_22d2:altsyncram1|ram_block3a0~porta_address_reg0 ; -- ; -- ; 121 ;
; Worst-case Minimum Pulse Width Requirement (High) ; -0.567 ns ; 3.067 ns ; 2.500 ns ; pll50:inst17|altpll:altpll_component|_clk0 ; rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_kod1:auto_generated|altsyncram_22d2:altsyncram1|ram_block3a0~porta_address_reg0 ; -- ; -- ; 121 ;
; Clock Setup: 'pll50:inst17|altpll:altpll_component|_clk0' ; -15.530 ns ; 200.00 MHz ( period = 5.000 ns ) ; 48.71 MHz ( period = 20.530 ns ) ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] ; CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|L_ACCDAT[4] ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 8940 ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A ; None ; 83.68 MHz ( period = 11.950 ns ) ; ram256:inst6|altsyncram:altsyncram_component|altsyncram_vbg1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out ; sld_hub:sld_hub_inst|hub_tdo_reg ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0 ;
; Clock Hold: 'pll50:inst17|altpll:altpll_component|_clk0' ; -7.266 ns ; 200.00 MHz ( period = 5.000 ns ) ; N/A ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|STX.st0 ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|STX.st0 ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 160 ;
; Other violations (see messages) ; ; ; ; ; ; ; ; 1 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 9343 ;
+-----------------------------------------------------------+------------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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