mcu8951.tan.summary

Alera 的8051 IP core的示例文件5个

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.998 ns
From           : P3I[0]
To             : CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|LDI_IN[0]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.325 ns
From           : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4]
To             : COUT
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 3.056 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 16.735 ns
From           : MT
To             : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|Q
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'pll50:inst17|altpll:altpll_component|_clk1'
Slack          : -23.720 ns
Required Time  : 12.00 MHz ( period = 83.333 ns )
Actual Time    : 7.65 MHz ( period = 130.774 ns )
From           : CNT32B:inst19|COUNTER10:inst6|74390:inst|32
To             : LOCK32:inst18|74374:inst8|19
From Clock     : pll50:inst17|altpll:altpll_component|_clk1
To Clock       : pll50:inst17|altpll:altpll_component|_clk1
Failed Paths   : 9

Type           : Clock Setup: 'pll50:inst17|altpll:altpll_component|_clk0'
Slack          : 29.063 ns
Required Time  : 12.00 MHz ( period = 83.333 ns )
Actual Time    : 39.67 MHz ( period = 25.206 ns )
From           : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|STX.ST12
To             : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|Q
From Clock     : pll50:inst17|altpll:altpll_component|_clk0
To Clock       : pll50:inst17|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 85.14 MHz ( period = 11.746 ns )
From           : ram256:inst6|altsyncram:altsyncram_component|altsyncram_omd1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'pll50:inst17|altpll:altpll_component|_clk1'
Slack          : -57.105 ns
Required Time  : 12.00 MHz ( period = 83.333 ns )
Actual Time    : N/A
From           : CNT32B:inst19|COUNTER10:inst6|74390:inst|32
To             : CNT32B:inst19|COUNTER10:inst6|74390:inst|32
From Clock     : pll50:inst17|altpll:altpll_component|_clk1
To Clock       : pll50:inst17|altpll:altpll_component|_clk1
Failed Paths   : 53

Type           : Clock Hold: 'pll50:inst17|altpll:altpll_component|_clk0'
Slack          : -9.607 ns
Required Time  : 12.00 MHz ( period = 83.333 ns )
Actual Time    : N/A
From           : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst10
To             : CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|STX.ST8
From Clock     : pll50:inst17|altpll:altpll_component|_clk0
To Clock       : pll50:inst17|altpll:altpll_component|_clk0
Failed Paths   : 154

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 216

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