clk_div.vhd

Alera 的8051 IP core的示例文件5个

library ieee; 
use ieee.std_logic_1164.all; 
 
entity clk_div is 
generic(n:integer:=3000000); 
    port (clock : in std_logic:='0'; 
          clk_out : out std_logic); 
end clk_div; 
 
architecture sea of clk_div is 
signal temp : std_logic:='0'; 
 
 
begin 
process(clock,temp) 
variable a,a1,a2 : integer range 0 to n; 
variable temp1,temp2 : std_logic:='0'; 
begin 
 
if (n rem 2)=1 then  
if rising_edge(clock) then 
    if a1=n-1 then a1:=0;temp1:='0'; 
    elsif a1<((n+1)/2-1) then temp1:='1';a1:=a1+1; 
       elsif a1>=((n+1)/2-1) then temp1:='0';a1:=a1+1; 
    end if; 
end if; 
if falling_edge(clock) then 
    if a2=n-1 then a2:=0;temp2:='0'; 
    elsif a2<((n+1)/2-1) then temp2:='1';a2:=a1+1; 
       elsif a2>=((n+1)/2-1) then temp2:='0';a2:=a2+1; 
    end if; 
end if; 
temp<=temp1 or temp2; 
elsif rising_edge(clock) then 
    if a=(n/2-1) then a:=0;temp<=not temp; 
    else a:=a+1; 
    end if; 
end if; 
 
end process; 
clk_out<=temp; 
end sea;