📄 mcu8951.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic
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-- without limitation, that your use is for the sole purpose of
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--Z1_CQI[4] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4] at LCFF_X17_Y7_N19
Z1_CQI[4] = DFFEAS(Z1L26, GLOBAL(R1L31), !R1L25, , , , , , );
--Z1_CQI[3] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3] at LCFF_X17_Y7_N17
Z1_CQI[3] = DFFEAS(Z1L21, GLOBAL(R1L31), !R1L25, , , , , , );
--Z1_CQI[5] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5] at LCFF_X17_Y7_N21
Z1_CQI[5] = DFFEAS(Z1L30, GLOBAL(R1L31), !R1L25, , , , , , );
--U1L1 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6E:inst3|LessThan0~74 at LCCOMB_X17_Y7_N24
U1L1 = !Z1_CQI[5] & (!Z1_CQI[4] # !Z1_CQI[3]);
--LB1_PORT3_SFR[7] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[7] at LCFF_X12_Y5_N19
LB1_PORT3_SFR[7] = DFFEAS(LB1L375, GLOBAL(UC1L2), RST, , , , , , );
--LB1_NRD is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|NRD at LCFF_X12_Y5_N9
LB1_NRD = DFFEAS(LB1L177, GLOBAL(UC1L2), , , , , , , );
--LB1_OD[7] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[7] at LCCOMB_X12_Y5_N20
LB1_OD[7] = LB1_NRD & !LB1_PORT3_SFR[7];
--LB1_PORT3_SFR[6] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[6] at LCFF_X21_Y7_N17
LB1_PORT3_SFR[6] = DFFEAS(LB1L370, GLOBAL(UC1L2), RST, , , , , , );
--LB1_NWR is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|NWR at LCFF_X21_Y7_N11
LB1_NWR = DFFEAS(LB1L182, GLOBAL(UC1L2), , , , , , , );
--LB1_OD[6] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[6] at LCCOMB_X21_Y7_N24
LB1_OD[6] = !LB1_PORT3_SFR[6] & LB1_NWR;
--LB1_PORT3_SFR[5] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[5] at LCFF_X20_Y8_N21
LB1_PORT3_SFR[5] = DFFEAS(LB1L365, GLOBAL(UC1L2), RST, , , , , , );
--LB1_PORT3_SFR[4] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[4] at LCFF_X24_Y5_N9
LB1_PORT3_SFR[4] = DFFEAS(LB1L360, GLOBAL(UC1L2), RST, , , , , , );
--LB1_PORT3_SFR[3] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[3] at LCFF_X24_Y5_N7
LB1_PORT3_SFR[3] = DFFEAS(LB1L352, GLOBAL(UC1L2), RST, , , , , , );
--LB1_PORT3_SFR[2] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[2] at LCFF_X17_Y6_N25
LB1_PORT3_SFR[2] = DFFEAS(LB1L347, GLOBAL(UC1L2), RST, , , , , , );
--QB1_TSEND is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|TSEND at LCFF_X21_Y11_N11
QB1_TSEND = DFFEAS(QB1L340, GLOBAL(UC1L2), , , , , , !P1_CLEAR, );
--QB1_TXCLK is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|TXCLK at LCFF_X21_Y11_N19
QB1_TXCLK = DFFEAS(QB1L359, GLOBAL(UC1L2), , , , , , , );
--QB1_L_SCON[6] is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|L_SCON[6] at LCFF_X22_Y10_N9
QB1_L_SCON[6] = DFFEAS(QB1L146, GLOBAL(UC1L2), , , , , , !P1_CLEAR, );
--QB1_L_SCON[7] is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|L_SCON[7] at LCFF_X22_Y10_N15
QB1_L_SCON[7] = DFFEAS(QB1L151, GLOBAL(UC1L2), , , , , , !P1_CLEAR, );
--QB1L169 is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|MODE0~0 at LCCOMB_X22_Y10_N0
QB1L169 = QB1_L_SCON[6] # QB1_L_SCON[7];
--QB1_RCV is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|RCV at LCFF_X22_Y12_N17
QB1_RCV = DFFEAS(QB1L215, GLOBAL(UC1L2), , , , , , , );
--LB1L188 is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~298 at LCCOMB_X21_Y11_N16
LB1L188 = QB1_TSEND & (!QB1L169 & QB1_TXCLK) # !QB1_TSEND & (!QB1L169 & QB1_TXCLK # !QB1_RCV);
--HC1_DAT[0] is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|m3s030bo:U9|DAT[0] at LCFF_X20_Y11_N15
HC1_DAT[0] = DFFEAS(HC1L5, GLOBAL(UC1L2), , , , , , !P1_CLEAR, );
--QB1_DATAEN is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|DATAEN at LCFF_X21_Y11_N5
QB1_DATAEN = DFFEAS(QB1L28, GLOBAL(UC1L2), , , , , , , );
--QB1_TXLASTBIT is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|TXLASTBIT at LCFF_X20_Y11_N31
QB1_TXLASTBIT = DFFEAS(QB1L381, GLOBAL(UC1L2), , , , , , , );
--LB1L191 is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~299 at LCCOMB_X21_Y11_N14
LB1L191 = QB1_TXLASTBIT # QB1_DATAEN & HC1_DAT[0] # !QB1_TSEND;
--LB1_PORT3_SFR[1] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[1] at LCFF_X17_Y6_N17
LB1_PORT3_SFR[1] = DFFEAS(LB1L342, GLOBAL(UC1L2), RST, , , , , , );
--LB1L194 is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~300 at LCCOMB_X21_Y10_N20
LB1L194 = !LB1_PORT3_SFR[1] & (LB1L188 # QB1L169 & LB1L191);
--LB1_PORT3_SFR[0] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[0] at LCFF_X21_Y7_N19
LB1_PORT3_SFR[0] = DFFEAS(LB1L337, GLOBAL(UC1L2), RST, , , , , , );
--LB1L185 is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[0]~301 at LCCOMB_X21_Y11_N24
LB1L185 = !LB1_PORT3_SFR[0] & (QB1L169 # HC1_DAT[0] # !QB1_TSEND);
--E1_B[0] is REG4:inst13|B[0] at LCFF_X12_Y5_N23
E1_B[0] = DFFEAS(UNCONNECTED_DATAIN, LB1_OD[7], , , , E1L3, , , VCC);
--E1_B[1] is REG4:inst13|B[1] at LCFF_X12_Y5_N31
E1_B[1] = DFFEAS(UNCONNECTED_DATAIN, LB1_OD[7], , , , E1L5, , , VCC);
--E1_B[2] is REG4:inst13|B[2] at LCFF_X12_Y5_N11
E1_B[2] = DFFEAS(UNCONNECTED_DATAIN, LB1_OD[7], , , , E1L7, , , VCC);
--E1_B[3] is REG4:inst13|B[3] at LCFF_X12_Y5_N29
E1_B[3] = DFFEAS(UNCONNECTED_DATAIN, LB1_OD[7], , , , E1L9, , , VCC);
--L1L7 is DECL7S:inst21|LED7S[6]~191 at LCCOMB_X12_Y5_N30
L1L7 = E1_B[0] & (E1_B[3] # E1_B[2] $ E1_B[1]) # !E1_B[0] & (E1_B[1] # E1_B[2] $ E1_B[3]);
--L1L6 is DECL7S:inst21|LED7S[5]~192 at LCCOMB_X12_Y5_N22
L1L6 = E1_B[2] & E1_B[0] & (E1_B[3] $ E1_B[1]) # !E1_B[2] & !E1_B[3] & (E1_B[0] # E1_B[1]);
--L1L5 is DECL7S:inst21|LED7S[4]~193 at LCCOMB_X12_Y5_N10
L1L5 = E1_B[1] & !E1_B[3] & (E1_B[0]) # !E1_B[1] & (E1_B[2] & !E1_B[3] # !E1_B[2] & (E1_B[0]));
--L1L4 is DECL7S:inst21|LED7S[3]~194 at LCCOMB_X12_Y5_N14
L1L4 = E1_B[1] & (E1_B[2] & (E1_B[0]) # !E1_B[2] & E1_B[3] & !E1_B[0]) # !E1_B[1] & !E1_B[3] & (E1_B[2] $ E1_B[0]);
--L1L3 is DECL7S:inst21|LED7S[2]~195 at LCCOMB_X12_Y5_N4
L1L3 = E1_B[2] & E1_B[3] & (E1_B[1] # !E1_B[0]) # !E1_B[2] & E1_B[1] & !E1_B[3] & !E1_B[0];
--L1L2 is DECL7S:inst21|LED7S[1]~196 at LCCOMB_X12_Y5_N28
L1L2 = E1_B[1] & (E1_B[0] & (E1_B[3]) # !E1_B[0] & E1_B[2]) # !E1_B[1] & E1_B[2] & (E1_B[3] $ E1_B[0]);
--L1L1 is DECL7S:inst21|LED7S[0]~197 at LCCOMB_X12_Y5_N16
L1L1 = E1_B[2] & !E1_B[1] & (E1_B[3] $ !E1_B[0]) # !E1_B[2] & E1_B[0] & (E1_B[1] $ !E1_B[3]);
--E2_B[3] is REG4:inst14|B[3] at LCFF_X9_Y5_N17
E2_B[3] = DFFEAS(E2L7, GLOBAL(LB1L200), , , , , , , );
--E2_B[2] is REG4:inst14|B[2] at LCFF_X8_Y5_N17
E2_B[2] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(LB1L200), , , , E1L7, , , VCC);
--E2_B[1] is REG4:inst14|B[1] at LCFF_X12_Y2_N9
E2_B[1] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(LB1L200), , , , E1L5, , , VCC);
--E2_B[0] is REG4:inst14|B[0] at LCFF_X10_Y5_N9
E2_B[0] = DFFEAS(E2L3, GLOBAL(LB1L200), , , , , , , );
--E3_B[3] is REG4:inst15|B[3] at LCFF_X20_Y8_N31
E3_B[3] = DFFEAS(E1L9, !LB1_PORT3_SFR[5], , , , , , , );
--E3_B[2] is REG4:inst15|B[2] at LCFF_X20_Y8_N7
E3_B[2] = DFFEAS(E1L7, !LB1_PORT3_SFR[5], , , , , , , );
--E3_B[1] is REG4:inst15|B[1] at LCFF_X20_Y8_N23
E3_B[1] = DFFEAS(E1L5, !LB1_PORT3_SFR[5], , , , , , , );
--E3_B[0] is REG4:inst15|B[0] at LCFF_X20_Y8_N9
E3_B[0] = DFFEAS(E1L3, !LB1_PORT3_SFR[5], , , , , , , );
--AB1_dffs[9] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] at LCFF_X2_Y5_N29
AB1_dffs[9] = DFFEAS(AB1L50, GLOBAL(R1L12), , , , , , , );
--AB1_dffs[6] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] at LCFF_X2_Y5_N19
AB1_dffs[6] = DFFEAS(AB1L35, GLOBAL(R1L12), , , , , , , );
--AB1_dffs[3] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] at LCFF_X2_Y5_N21
AB1_dffs[3] = DFFEAS(AB1L20, GLOBAL(R1L12), , , , , , , );
--Y1L1 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|XOR3:inst33|1~13 at LCCOMB_X2_Y5_N26
Y1L1 = AB1_dffs[3] $ AB1_dffs[6] $ AB1_dffs[9];
--B1_inst19 is CPU8051V1:inst|inst19 at LCFF_X4_Y6_N5
B1_inst19 = DFFEAS(B1L9, B1_inst9, , , , , , , );
--R1_inst10 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst10 at LCFF_X5_Y6_N31
R1_inst10 = DFFEAS(R1L8, X1_Equal0, !S1_inst, , , , , , );
--R1_inst15 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst15 at LCCOMB_X4_Y6_N30
R1_inst15 = B1_inst19 & !R1_inst10;
--AB1_dffs[4] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] at LCFF_X2_Y5_N1
AB1_dffs[4] = DFFEAS(AB1L25, GLOBAL(R1L12), , , , , , , );
--AB1_dffs[8] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] at LCFF_X2_Y5_N11
AB1_dffs[8] = DFFEAS(AB1L45, GLOBAL(R1L12), , , , , , , );
--AB1_dffs[1] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] at LCFF_X2_Y5_N13
AB1_dffs[1] = DFFEAS(AB1L10, GLOBAL(R1L12), , , , , , , );
--Y2_1 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|XOR3:inst34|1 at LCCOMB_X2_Y5_N16
Y2_1 = AB1_dffs[1] $ AB1_dffs[4] $ AB1_dffs[8];
--AB1_dffs[23] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[23] at LCFF_X1_Y4_N31
AB1_dffs[23] = DFFEAS(AB1L120, GLOBAL(R1L12), , , , , , , );
--A1L7 is altera_internal_jtag~TDO at JTAG_X1_Y7_N0
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , M1L20);
--A1L8 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y7_N0
A1L8 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , M1L20);
--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y7_N0
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , M1L20);
--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y7_N0
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , M1L20);
--R1_inst5 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst5 at LCFF_X2_Y6_N7
R1_inst5 = DFFEAS(R1L4, GLOBAL(R1L12), , , , , , , );
--R1_inst18 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst18 at LCCOMB_X2_Y6_N30
R1_inst18 = MT $ R1_inst5;
--R1_inst19 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst19 at LCFF_X1_Y6_N3
R1_inst19 = DFFEAS(R1L17, GLOBAL(R1L12), , , , , , , );
--R1_inst20 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst20 at LCCOMB_X1_Y6_N0
R1_inst20 = NO $ R1_inst19;
--R1_inst24 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst24 at LCCOMB_X1_Y6_N20
R1_inst24 = !R1_inst10 & !R1_inst18 & R1_inst15 & !R1_inst20;
--Z1_CQI[2] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[2] at LCFF_X17_Y7_N15
Z1_CQI[2] = DFFEAS(Z1L16, GLOBAL(R1L31), !R1L25, , , , , , );
--Z1_CQI[0] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[0] at LCFF_X17_Y7_N27
Z1_CQI[0] = DFFEAS(Z1L5, GLOBAL(R1L31), !R1L25, , , , , , );
--Z1_CQI[1] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[1] at LCFF_X17_Y7_N13
Z1_CQI[1] = DFFEAS(Z1L11, GLOBAL(R1L31), !R1L25, , , , , , );
--Z1L11 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[1]~ICOMBOUT at LCCOMB_X17_Y7_N12
Z1L11 = Z1_CQI[1] & (Z1_CQI[0] $ VCC) # !Z1_CQI[1] & Z1_CQI[0] & VCC;
--Z1L9 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[1]~36 at LCCOMB_X17_Y7_N12
Z1L9 = CARRY(Z1_CQI[1] & Z1_CQI[0]);
--Z1L16 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[2]~ICOMBOUT at LCCOMB_X17_Y7_N14
Z1L16 = Z1_CQI[2] & !Z1L9 # !Z1_CQI[2] & (Z1L9 # GND);
--Z1L14 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[2]~34 at LCCOMB_X17_Y7_N14
Z1L14 = CARRY(!Z1L9 # !Z1_CQI[2]);
--Z1L21 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3]~ICOMBOUT at LCCOMB_X17_Y7_N16
Z1L21 = Z1_CQI[3] & (Z1L14 $ GND) # !Z1_CQI[3] & !Z1L14 & VCC;
--Z1L19 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3]~28 at LCCOMB_X17_Y7_N16
Z1L19 = CARRY(Z1_CQI[3] & !Z1L14);
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