mcu8951.tan.rpt

Alera 的8051 IP core的示例文件5个

; Type                                                      ; Slack      ; Required Time                    ; Actual Time                      ; From                                                                                                                      ; To                                                           ; From Clock                                 ; To Clock                                   ; Failed Paths ;
+-----------------------------------------------------------+------------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+
; Worst-case tsu                                            ; N/A        ; None                             ; 7.998 ns                         ; P3I[0]                                                                                                                    ; CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|LDI_IN[0]         ; --                                         ; CLK                                        ; 0            ;
; Worst-case tco                                            ; N/A        ; None                             ; 21.325 ns                        ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4]                                                                ; COUT                                                         ; CLK                                        ; --                                         ; 0            ;
; Worst-case tpd                                            ; N/A        ; None                             ; 3.056 ns                         ; altera_internal_jtag~TDO                                                                                                  ; altera_reserved_tdo                                          ; --                                         ; --                                         ; 0            ;
; Worst-case th                                             ; N/A        ; None                             ; 16.735 ns                        ; MT                                                                                                                        ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|Q       ; --                                         ; CLK                                        ; 0            ;
; Clock Setup: 'pll50:inst17|altpll:altpll_component|_clk1' ; -23.720 ns ; 12.00 MHz ( period = 83.333 ns ) ; 7.65 MHz ( period = 130.774 ns ) ; CNT32B:inst19|COUNTER10:inst6|74390:inst|32                                                                               ; LOCK32:inst18|74374:inst8|19                                 ; pll50:inst17|altpll:altpll_component|_clk1 ; pll50:inst17|altpll:altpll_component|_clk1 ; 9            ;
; Clock Setup: 'pll50:inst17|altpll:altpll_component|_clk0' ; 29.063 ns  ; 12.00 MHz ( period = 83.333 ns ) ; 39.67 MHz ( period = 25.206 ns ) ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|STX.ST12                                                             ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|Q       ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'               ; N/A        ; None                             ; 85.14 MHz ( period = 11.746 ns ) ; ram256:inst6|altsyncram:altsyncram_component|altsyncram_omd1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; sld_hub:sld_hub_inst|hub_tdo                                 ; altera_internal_jtag~TCKUTAP               ; altera_internal_jtag~TCKUTAP               ; 0            ;
; Clock Hold: 'pll50:inst17|altpll:altpll_component|_clk1'  ; -57.105 ns ; 12.00 MHz ( period = 83.333 ns ) ; N/A                              ; CNT32B:inst19|COUNTER10:inst6|74390:inst|32                                                                               ; CNT32B:inst19|COUNTER10:inst6|74390:inst|32                  ; pll50:inst17|altpll:altpll_component|_clk1 ; pll50:inst17|altpll:altpll_component|_clk1 ; 53           ;
; Clock Hold: 'pll50:inst17|altpll:altpll_component|_clk0'  ; -9.607 ns  ; 12.00 MHz ( period = 83.333 ns ) ; N/A                              ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst10                                                                             ; CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|MEALY1:inst14|STX.ST8 ; pll50:inst17|altpll:altpll_component|_clk0 ; pll50:inst17|altpll:altpll_component|_clk0 ; 154          ;
; Total number of failed paths                              ;            ;                                  ;                                  ;                                                                                                                           ;                                                              ;                                            ;                                            ; 216          ;
+-----------------------------------------------------------+------------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C5T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll50:inst17|altpll:altpll_component|_clk0 ;                    ; PLL output ; 12.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK      ; 3                     ; 5                   ; -2.243 ns ;              ;