mcu8951.map.eqn

Alera 的8051 IP core的示例文件5个

--RB1L4 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U1|P~276
RB1L4 = FB1_TMPDAT[0] & (EB1_ACLDAT[0] & (!UB1L68) # !EB1_ACLDAT[0] & UB1L20);


--RB1L10 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U1|P~278
RB1L10 = RB1L4 # !FB1_TMPDAT[0] & RB1L7;


--SB1L7 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s041bo:U9|S~1213
SB1L7 = RB6L4 & RB8L4 & CB1L241 & RB1L10;


--CB1_CBEN is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CBEN
CB1_CBEN = UB1L26 # !UB1L29;


--SB1L10 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s041bo:U9|S~1214
SB1L10 = SB1L7 # CB1_CBEN & (CB1L130 # SB1L4);


--EB1_ACC0 is CPU8051V1:inst|MCU80512:inst3|m3s005bo:U4|ACC0
EB1_ACC0 = DFFEAS(EB1L4, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--UB1_AJ is CPU8051V1:inst|MCU80512:inst3|m3s004bo:U3|m3s024bo:U2|AJ
UB1_AJ = TB1L46 # TB1L10;


--FB1_TMPDAT[7] is CPU8051V1:inst|MCU80512:inst3|m3s006bo:U5|TMPDAT[7]
FB1_TMPDAT[7] = DFFEAS(FB1L52, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--CB1L100 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|DB~930
CB1L100 = EB1_ACLDAT[7] & (FB1_TMPDAT[7] & (UB1L26) # !FB1_TMPDAT[7] & !UB1L29);


--RB7L1 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U8|P~475
RB7L1 = EB1_ACLDAT[7] & (FB1_TMPDAT[7] # !UB1L74) # !EB1_ACLDAT[7] & (!FB1_TMPDAT[7] & UB1_ALUC[0]);


--RB7L4 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U8|P~476
RB7L4 = FB1_TMPDAT[7] & (RB7L1 & !UB1L68 # !RB7L1 & (UB1L20)) # !FB1_TMPDAT[7] & (RB7L1);


--FB1_TMPDAT[6] is CPU8051V1:inst|MCU80512:inst3|m3s006bo:U5|TMPDAT[6]
FB1_TMPDAT[6] = DFFEAS(FB1L47, UC1__clk0, RST,  ,  , FB1_TMPDAT[6],  ,  , FB1L153);


--RB4L1 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U7|P~278
RB4L1 = FB1_TMPDAT[6] & (UB1L68 # !EB1_ACLDAT[6]) # !FB1_TMPDAT[6] & EB1_ACLDAT[6] & UB1L74;


--RB4L4 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U7|P~279
RB4L4 = EB1_ACLDAT[6] & (!RB4L1) # !EB1_ACLDAT[6] & (RB4L1 & (UB1L20) # !RB4L1 & UB1_ALUC[0]);


--CB1L106 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|DB~932
CB1L106 = FB1_TMPDAT[6] & (UB1L26) # !FB1_TMPDAT[6] & !UB1L29;


--FB1_TMPDAT[5] is CPU8051V1:inst|MCU80512:inst3|m3s006bo:U5|TMPDAT[5]
FB1_TMPDAT[5] = DFFEAS(FB1L33, UC1__clk0, RST,  ,  , FB1_TMPDAT[5],  ,  , FB1L153);


--SB2L4 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s041bo:U10|S~1209
SB2L4 = EB1_ACLDAT[5] & (FB1_TMPDAT[5] & (UB1L26) # !FB1_TMPDAT[5] & !UB1L29);


--RB2L1 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U6|P~283
RB2L1 = FB1_TMPDAT[5] & (UB1L68 # !EB1_ACLDAT[5]) # !FB1_TMPDAT[5] & EB1_ACLDAT[5] & UB1L74;


--RB2L4 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U6|P~284
RB2L4 = EB1_ACLDAT[5] & (!RB2L1) # !EB1_ACLDAT[5] & (RB2L1 & (UB1L20) # !RB2L1 & UB1_ALUC[0]);


--FB1_TMPDAT[4] is CPU8051V1:inst|MCU80512:inst3|m3s006bo:U5|TMPDAT[4]
FB1_TMPDAT[4] = DFFEAS(FB1L28, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--RB3_CO is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U5|CO
RB3_CO = EB1_ACLDAT[4] & (FB1_TMPDAT[4] & (UB1L26) # !FB1_TMPDAT[4] & !UB1L29);


--SB2L7 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s041bo:U10|S~1210
SB2L7 = SB2L4 # RB2L4 & RB3_CO;


--SB2L10 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s041bo:U10|S~1211
SB2L10 = EB1_ACLDAT[6] & !CB1L106 & (!SB2L7 # !RB4L4) # !EB1_ACLDAT[6] & (!SB2L7 # !RB4L4);


--RB3L4 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U5|P~283
RB3L4 = FB1_TMPDAT[4] & (UB1L68 # !EB1_ACLDAT[4]) # !FB1_TMPDAT[4] & EB1_ACLDAT[4] & (UB1L74);


--RB3L7 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s002bo:U5|P~284
RB3L7 = EB1_ACLDAT[4] & (!RB3L4) # !EB1_ACLDAT[4] & (RB3L4 & (UB1L20) # !RB3L4 & UB1_ALUC[0]);


--CB1L124 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|GEN_LO~784
CB1L124 = FB1_TMPDAT[3] & (UB1L26) # !FB1_TMPDAT[3] & !UB1L29;


--CB1L61 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CA~72
CB1L61 = EB1_ACLDAT[3] & !CB1L124 & (!SB1L4 # !RB5L4) # !EB1_ACLDAT[3] & (!SB1L4 # !RB5L4);


--CB1L64 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CA~73
CB1L64 = CB1L61 & (!CB1L130 & !SB1L7 # !RB5L4);


--CB1L103 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|DB~931
CB1L103 = RB2L4 & RB4L4 & RB3L7 & !CB1L64;


--CB1L109 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|DB~933
CB1L109 = CB1L100 # RB7L4 & (CB1L103 # !SB2L10);


--CB1L70 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CMUX~60
CB1L70 = EB1_ACC0 & (UB1_AC # CB1L109) # !EB1_ACC0 & UB1_AJ & (UB1_AC # CB1L109);


--CB1L82 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CPRDDM[3]~2119
CB1L82 = CB1L70 & (RB5L4 $ SB1L10) # !CB1L70 & EB1_ACLDAT[3];


--UB1L92 is CPU8051V1:inst|MCU80512:inst3|m3s004bo:U3|m3s024bo:U2|AP~27
UB1L92 = !PB1_OPC[6] & !TB1L43 & !PB1_OPC[5] & !PB1_OPC[7];


--UB1_ALUC[6] is CPU8051V1:inst|MCU80512:inst3|m3s004bo:U3|m3s024bo:U2|ALUC[6]
UB1_ALUC[6] = UB1L92 # !TB1L46 & (!TB1L10 # !TB1L16);


--UB1L35 is CPU8051V1:inst|MCU80512:inst3|m3s004bo:U3|m3s024bo:U2|ALUC[7]~2055
UB1L35 = PB1_OPC[7] & !PB1_OPC[4] & !TB1L46 & !PB1_OPC[5];


--UB1L38 is CPU8051V1:inst|MCU80512:inst3|m3s004bo:U3|m3s024bo:U2|ALUC[7]~2056
UB1L38 = UB1L35 # PB1_OPC[5] & DB1L84 & !TB1L43;


--SB2L13 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s041bo:U10|S~1212
SB2L13 = RB2L4 & RB3L7 & CB1_CBEN & !CB1L64;


--SB2L19 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s041bo:U10|S~1214
SB2L19 = SB2L13 # SB2L7 & (UB1L26 # !UB1L29);


--CB1L91 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CPRDDM[6]~2118
CB1L91 = CB1L70 & (RB4L4 $ (SB2L19)) # !CB1L70 & (EB1_ACLDAT[6]);


--SB2L16 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|m3s041bo:U10|S~1213
SB2L16 = RB4L4 & (SB2L13 # !SB2L10 & CB1_CBEN) # !RB4L4 & !SB2L10 & CB1_CBEN;


--CB1L94 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CPRDDM[7]~2117
CB1L94 = CB1L70 & (RB7L4 $ SB2L16) # !CB1L70 & EB1_ACLDAT[7];


--CB1L148 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|Mux0~12
CB1L148 = UB1L38 & (CB1L91 # UB1_ALUC[6]) # !UB1L38 & (CB1L94 & !UB1_ALUC[6]);


--CB1L73 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CPRDDM[0]~2116
CB1L73 = CB1L70 & (RB1L10 $ (CB1L241)) # !CB1L70 & (EB1_ACLDAT[0]);


--UB1_ALUC[15] is CPU8051V1:inst|MCU80512:inst3|m3s004bo:U3|m3s024bo:U2|ALUC[15]
UB1_ALUC[15] = PB1_OPC[4] & DB1L84 & !TB1L43 # !UB1_AJ;


--CB1_CARI is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|CARI
CB1_CARI = CB1L109 $ (!UB1L29 & (TB1L46 # !TB1L31));


--CB1L142 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|LOCALD~124
CB1L142 = UB1_AJ & EB1_ACLDAT[9] # !UB1_AJ & (EB1_ACC0 & CB1_CARI);


--CB1L145 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|LOCALD~125
CB1L145 = UB1_ALUC[15] & (CB1L142) # !UB1_ALUC[15] & CB1L73;


--CB1L151 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|Mux0~13
CB1L151 = UB1_ALUC[6] & (CB1L148 & CB1L82 # !CB1L148 & (CB1L145)) # !UB1_ALUC[6] & (CB1L148);


--JB1L39 is CPU8051V1:inst|MCU80512:inst3|m3s010bo:U8|ADDR_16BIT_LOW[7]~COMBOUT
JB1L39 = CB1L217 & CB1L43 # !CB1L217 & (CB1L151);


--HB1L497 is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|RAMDI~587
HB1L497 = YB1_REGADD[9] & JB1_STACK_DATA[15] & (!HB1L473) # !YB1_REGADD[9] & (JB1L39 # HB1L473);


--HB1L500 is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|RAMDI~588
HB1L500 = HB1L473 & (HB1L497 & (P1_IMMDAT[7]) # !HB1L497 & JB1_STACK_DATA[7]) # !HB1L473 & (HB1L497);


--HB1L495 is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|RAMDI[7]~ICOMBOUT
HB1L495 = HB1L476 & (HB1L500) # !HB1L476 & ZB1_REG_HI_NIBBLE[7];


--NB1_L_PCON[0] is CPU8051V1:inst|MCU80512:inst3|m3s020bo:U12|L_PCON[0]
NB1_L_PCON[0] = DFFEAS(NB1L58, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--BB1L24 is CPU8051V1:inst|MCU80512:inst3|m3s001bo:U1|LDV2CK2~ICOMBOUT
BB1L24 = NB1_L_PCON[0] # !BB1_LDV2CK1;


--HB1_SEL_INDADDR is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|SEL_INDADDR
HB1_SEL_INDADDR = DFFEAS(HB1L796, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--HB1_SEL_STACKPTR is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|SEL_STACKPTR
HB1_SEL_STACKPTR = DFFEAS(HB1L829, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--HB1_INDIRECT_ADDR[6] is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|INDIRECT_ADDR[6]
HB1_INDIRECT_ADDR[6] = DFFEAS(HB1L74, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--FC1_L_SP[6] is CPU8051V1:inst|MCU80512:inst3|m3s020bo:U12|m3s014bo:U1|L_SP[6]
FC1_L_SP[6] = DFFEAS(FC1L77, UC1__clk0,  ,  ,  ,  ,  , !P1_CLEAR,  );


--HB1L128 is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA~2039
HB1L128 = HB1_SEL_INDADDR & (HB1_INDIRECT_ADDR[6] # HB1_SEL_STACKPTR & FC1_L_SP[6]) # !HB1_SEL_INDADDR & HB1_SEL_STACKPTR & (FC1_L_SP[6]);


--YB1L44 is CPU8051V1:inst|MCU80512:inst3|m3s004bo:U3|m3s035bo:U6|REGADD[10]~1196
YB1L44 = !UB1L89 & (TB1L10 # TB1L40);


--CB1L46 is CPU8051V1:inst|MCU80512:inst3|m3s003bo:U2|BC~1359
CB1L46 = PB1_OPC[5] & !PB1_OPC[6];


--HB1_SEL_DIRADDR is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|SEL_DIRADDR
HB1_SEL_DIRADDR = DFFEAS(HB1L785, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--HB1L122 is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|L_FA~2037
HB1L122 = YB1L44 & !HB1_SEL_DIRADDR & (TB1L34 # !CB1L46);


--MC1_q_a[7] is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_uu21:auto_generated|altsyncram_doe2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 4096, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_a[7]_PORT_A_data_in = VCC;
MC1_q_a[7]_PORT_A_data_in_reg = DFFE(MC1_q_a[7]_PORT_A_data_in, MC1_q_a[7]_clock_0, , , );
MC1_q_a[7]_PORT_B_data_in = NC2_ram_rom_data_reg[7];
MC1_q_a[7]_PORT_B_data_in_reg = DFFE(MC1_q_a[7]_PORT_B_data_in, MC1_q_a[7]_clock_1, , , );
MC1_q_a[7]_PORT_A_address = BUS(JB1_PROGRAM_ADDR[0], JB1_PROGRAM_ADDR[1], JB1_PROGRAM_ADDR[2], JB1_PROGRAM_ADDR[3], JB1_PROGRAM_ADDR[4], JB1_PROGRAM_ADDR[5], JB1_PROGRAM_ADDR[6], JB1_PROGRAM_ADDR[7], JB1_PROGRAM_ADDR[8], JB1_PROGRAM_ADDR[9], JB1_PROGRAM_ADDR[10], JB1_PROGRAM_ADDR[11]);
MC1_q_a[7]_PORT_A_address_reg = DFFE(MC1_q_a[7]_PORT_A_address, MC1_q_a[7]_clock_0, , , );
MC1_q_a[7]_PORT_B_address = BUS(NC2_ram_rom_addr_reg[0], NC2_ram_rom_addr_reg[1], NC2_ram_rom_addr_reg[2], NC2_ram_rom_addr_reg[3], NC2_ram_rom_addr_reg[4], NC2_ram_rom_addr_reg[5], NC2_ram_rom_addr_reg[6], NC2_ram_rom_addr_reg[7], NC2_ram_rom_addr_reg[8], NC2_ram_rom_addr_reg[9], NC2_ram_rom_addr_reg[10], NC2_ram_rom_addr_reg[11]);
MC1_q_a[7]_PORT_B_address_reg = DFFE(MC1_q_a[7]_PORT_B_address, MC1_q_a[7]_clock_1, , , );
MC1_q_a[7]_PORT_A_write_enable = GND;
MC1_q_a[7]_PORT_A_write_enable_reg = DFFE(MC1_q_a[7]_PORT_A_write_enable, MC1_q_a[7]_clock_0, , , );
MC1_q_a[7]_PORT_B_write_enable = NC2L3;
MC1_q_a[7]_PORT_B_write_enable_reg = DFFE(MC1_q_a[7]_PORT_B_write_enable, MC1_q_a[7]_clock_1, , , );
MC1_q_a[7]_clock_0 = UC1__clk0;
MC1_q_a[7]_clock_1 = A1L5;
MC1_q_a[7]_PORT_A_data_out = MEMORY(MC1_q_a[7]_PORT_A_data_in_reg, MC1_q_a[7]_PORT_B_data_in_reg, MC1_q_a[7]_PORT_A_address_reg, MC1_q_a[7]_PORT_B_address_reg, MC1_q_a[7]_PORT_A_write_enable_reg, MC1_q_a[7]_PORT_B_write_enable_reg, , , MC1_q_a[7]_clock_0, MC1_q_a[7]_clock_1, , , , );
MC1_q_a[7] = MC1_q_a[7]_PORT_A_data_out[0];

--MC1_q_b[7] is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_uu21:auto_generated|altsyncram_doe2:altsyncram1|q_b[7]
MC1_q_b[7]_PORT_A_data_in = VCC;
MC1_q_b[7]_PORT_A_data_in_reg = DFFE(MC1_q_b[7]_PORT_A_data_in, MC1_q_b[7]_clock_0, , , );
MC1_q_b[7]_PORT_B_data_in = NC2_ram_rom_data_reg[7];
MC1_q_b[7]_PORT_B_data_in_reg = DFFE(MC1_q_b[7]_PORT_B_data_in, MC1_q_b[7]_clock_1, , , );
MC1_q_b[7]_PORT_A_address = BUS(JB1_PROGRAM_ADDR[0], JB1_PROGRAM_ADDR[1], JB1_PROGRAM_ADDR[2], JB1_PROGRAM_ADDR[3], JB1_PROGRAM_ADDR[4], JB1_PROGRAM_ADDR[5], JB1_PROGRAM_ADDR[6], JB1_PROGRAM_ADDR[7], JB1_PROGRAM_ADDR[8], JB1_PROGRAM_ADDR[9], JB1_PROGRAM_ADDR[10], JB1_PROGRAM_ADDR[11]);
MC1_q_b[7]_PORT_A_address_reg = DFFE(MC1_q_b[7]_PORT_A_address, MC1_q_b[7]_clock_0, , , );
MC1_q_b[7]_PORT_B_address = BUS(NC2_ram_rom_addr_reg[0], NC2_ram_rom_addr_reg[1], NC2_ram_rom_addr_reg[2], NC2_ram_rom_addr_reg[3], NC2_ram_rom_addr_reg[4], NC2_ram_rom_addr_reg[5], NC2_ram_rom_addr_reg[6], NC2_ram_rom_addr_reg[7], NC2_ram_rom_addr_reg[8], NC2_ram_rom_addr_reg[9], NC2_ram_rom_addr_reg[10], NC2_ram_rom_addr_reg[11]);
MC1_q_b[7]_PORT_B_address_reg = DFFE(MC1_q_b[7]_PORT_B_address, MC1_q_b[7]_clock_1, , , );
MC1_q_b[7]_PORT_A_write_enable = GND;
MC1_q_b[7]_PORT_A_write_enable_reg = DFFE(MC1_q_b[7]_PORT_A_write_enable, MC1_q_b[7]_clock_0, , , );
MC1_q_b[7]_PORT_B_write_enable = NC2L3;
MC1_q_b[7]_PORT_B_write_enable_reg = DFFE(MC1_q_b[7]_PORT_B_write_enable, MC1_q_b[7]_clock_1, , , );
MC1_q_b[7]_clock_0 = UC1__clk0;
MC1_q_b[7]_clock_1 = A1L5;
MC1_q_b[7]_PORT_B_data_out = MEMORY(MC1_q_b[7]_PORT_A_data_in_reg, MC1_q_b[7]_PORT_B_data_in_reg, MC1_q_b[7]_PORT_A_address_reg, MC1_q_b[7]_PORT_B_address_reg, MC1_q_b[7]_PORT_A_write_enable_reg, MC1_q_b[7]_PORT_B_write_enable_reg, , , MC1_q_b[7]_clock_0, MC1_q_b[7]_clock_1, , , , );
MC1_q_b[7] = MC1_q_b[7]_PORT_B_data_out[0];


--P1L101 is CPU8051V1:inst|MCU80512:inst3|IROMD[7]~128
P1L101 = MC1_q_a[7] & !U1L1;


--LB1_L_EXPMEM is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|L_EXPMEM
LB1_L_EXPMEM = DFFEAS(LB1L168, UC1__clk0, RST,  ,  , LB1_L_EXPMEM,  ,  , !BB1_LDV2CK2);


--DB1L4 is CPU8051V1:inst|MCU80512:inst3|m3s004bo:U3|AJ~17
DB1L4 = !PB1_OPC[2] & PB1_OPC[1] & !PB1_OPC[3];


--P1L104 is CPU8051V1:inst|MCU80512:inst3|OA[2]~1923
P1L104 = PB1_OPC[5] & PB1_OPC[6] & PB1_OPC[7];


--P1L110 is CPU8051V1:inst|MCU80512:inst3|muxiromd~49
P1L110 = BB1_STATD[3] & P1L104 & (DB1L4 # !TB1L34);


--P1L107 is CPU8051V1:inst|MCU80512:inst3|muxiromd~1
P1L107 = LB1_L_EXPMEM # P1L110;


--P1L77 is CPU8051V1:inst|MCU80512:inst3|IMMDAT[7]~COMBOUT
P1L77 = P1L101 & !P1L107;


--HB1L1 is CPU8051V1:inst|MCU80512:inst3|m3s008bo:U7|BIT_MODE_ADDR[7]~77
HB1L1 = BB1_Q4 & (BB1_Q5 & (P1L77) # !BB1_Q5 & P1_IMMDAT[7]) # !BB1_Q4 & (P1L77);


--P1_IMMDAT[6] is CPU8051V1:inst|MCU80512:inst3|IMMDAT[6]
P1_IMMDAT[6] = DFFEAS(P1L72, UC1__clk0,  ,  ,  , P1_IMMDAT[6],  ,  , P1L34);


--MC1_q_a[6] is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_uu21:auto_generated|altsyncram_doe2:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 4096, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_a[6]_PORT_A_data_in = VCC;
MC1_q_a[6]_PORT_A_data_in_reg = DFFE(MC1_q_a[6]_PORT_A_data_in, MC1_q_a[6]_clock_0, , , );
MC1_q_a[6]_PORT_B_data_in = NC2_ram_rom_data_reg[6];
MC1_q_a[6]_PORT_B_data_in_reg = DFFE(MC1_q_a[6]_PORT_B_data_in, MC1_q_a[6]_clock_1, , , );
MC1_q_a[6]_PORT_A_address = BUS(JB1_PROGRAM_ADDR[0], JB1_PROGRAM_ADDR[1], JB1_PROGRAM_ADDR[2], JB1_PROGRAM_ADDR[3], JB1_PROGRAM_ADDR[4], JB1_PROGRAM_ADDR[5], JB1_PROGRAM_ADDR[6], JB1_PROGRAM_ADDR[7], JB1_PROGRAM_ADDR[8], JB1_PROGRAM_ADDR[9], JB1_PROGRAM_ADDR[10], JB1_PROGRAM_ADDR[11]);
MC1_q_a[6]_PORT_A_address_reg = DFFE(MC1_q_a[6]_PORT_A_address, MC1_q_a[6]_clock_0, , , );
MC1_q_a[6]_PORT_B_address = BUS(NC2_ram_rom_addr_reg[0], NC2_ram_rom_addr_reg[1], NC2_ram_rom_addr_reg[2], NC2_ram_rom_addr_reg[3], NC2_ram_rom_addr_reg[4], NC2_ram_rom_addr_reg[5], NC2_ram_rom_addr_reg[6], NC2_ram_rom_addr_reg[7], NC2_ram_rom_addr_reg[8], NC2_ram_rom_addr_reg[9], NC2_ram_rom_addr_reg[10], NC2_ram_rom_addr_reg[11]);
MC1_q_a[6]_PORT_B_address_reg = DFFE(MC1_q_a[6]_PORT_B_address, MC1_q_a[6]_clock_1, , , );
MC1_q_a[6]_PORT_A_write_enable = GND;
MC1_q_a[6]_PORT_A_write_enable_reg = DFFE(MC1_q_a