mcu8951.map.eqn

Alera 的8051 IP core的示例文件5个

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--Z1_CQI[4] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4]
Z1_CQI[4] = DFFEAS(Z1L26, R1_inst24, !R1L23,  ,  ,  ,  ,  ,  );


--Z1_CQI[3] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3]
Z1_CQI[3] = DFFEAS(Z1L21, R1_inst24, !R1L23,  ,  ,  ,  ,  ,  );


--Z1_CQI[5] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5]
Z1_CQI[5] = DFFEAS(Z1L30, R1_inst24, !R1L23,  ,  ,  ,  ,  ,  );


--U1L1 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6E:inst3|LessThan0~74
U1L1 = !Z1_CQI[5] & (!Z1_CQI[3] # !Z1_CQI[4]);


--LB1_PORT3_SFR[7] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[7]
LB1_PORT3_SFR[7] = DFFEAS(LB1L376, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--LB1_NRD is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|NRD
LB1_NRD = DFFEAS(LB1L179, UC1__clk0,  ,  ,  ,  ,  ,  ,  );


--LB1_OD[7] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[7]
LB1_OD[7] = !LB1_PORT3_SFR[7] & LB1_NRD;


--LB1_PORT3_SFR[6] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[6]
LB1_PORT3_SFR[6] = DFFEAS(LB1L371, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--LB1_NWR is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|NWR
LB1_NWR = DFFEAS(LB1L184, UC1__clk0,  ,  ,  ,  ,  ,  ,  );


--LB1_OD[6] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[6]
LB1_OD[6] = !LB1_PORT3_SFR[6] & LB1_NWR;


--LB1_PORT3_SFR[5] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[5]
LB1_PORT3_SFR[5] = DFFEAS(LB1L366, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--LB1_PORT3_SFR[4] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[4]
LB1_PORT3_SFR[4] = DFFEAS(LB1L361, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--LB1_PORT3_SFR[3] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[3]
LB1_PORT3_SFR[3] = DFFEAS(LB1L353, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--LB1_PORT3_SFR[2] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[2]
LB1_PORT3_SFR[2] = DFFEAS(LB1L348, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--QB1_TSEND is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|TSEND
QB1_TSEND = DFFEAS(QB1L346, UC1__clk0,  ,  ,  ,  ,  , !P1_CLEAR,  );


--QB1_TXCLK is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|TXCLK
QB1_TXCLK = DFFEAS(QB1L365, UC1__clk0,  ,  ,  ,  ,  ,  ,  );


--QB1_L_SCON[6] is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|L_SCON[6]
QB1_L_SCON[6] = DFFEAS(QB1L146, UC1__clk0,  ,  ,  ,  ,  , !P1_CLEAR,  );


--QB1_L_SCON[7] is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|L_SCON[7]
QB1_L_SCON[7] = DFFEAS(QB1L151, UC1__clk0,  ,  ,  ,  ,  , !P1_CLEAR,  );


--QB1L169 is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|MODE0~0
QB1L169 = QB1_L_SCON[6] # QB1_L_SCON[7];


--QB1_RCV is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|RCV
QB1_RCV = DFFEAS(QB1L215, UC1__clk0,  ,  ,  ,  ,  ,  ,  );


--LB1L190 is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~298
LB1L190 = QB1_TSEND & QB1_TXCLK & !QB1L169 # !QB1_TSEND & (QB1_TXCLK & !QB1L169 # !QB1_RCV);


--HC1_DAT[0] is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|m3s030bo:U9|DAT[0]
HC1_DAT[0] = DFFEAS(HC1L5, UC1__clk0,  ,  ,  ,  ,  , !P1_CLEAR,  );


--QB1_DATAEN is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|DATAEN
QB1_DATAEN = DFFEAS(QB1L28, UC1__clk0,  ,  ,  ,  ,  ,  ,  );


--QB1_TXLASTBIT is CPU8051V1:inst|MCU80512:inst3|m3s028bo:U15|TXLASTBIT
QB1_TXLASTBIT = DFFEAS(QB1L387, UC1__clk0,  ,  ,  ,  ,  ,  ,  );


--LB1L193 is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~299
LB1L193 = QB1_TXLASTBIT # HC1_DAT[0] & QB1_DATAEN # !QB1_TSEND;


--LB1_PORT3_SFR[1] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[1]
LB1_PORT3_SFR[1] = DFFEAS(LB1L343, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--LB1L196 is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~300
LB1L196 = !LB1_PORT3_SFR[1] & (LB1L190 # LB1L193 & QB1L169);


--LB1_PORT3_SFR[0] is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[0]
LB1_PORT3_SFR[0] = DFFEAS(LB1L338, UC1__clk0, RST,  ,  ,  ,  ,  ,  );


--LB1L187 is CPU8051V1:inst|MCU80512:inst3|m3s018bo:U10|OD[0]~301
LB1L187 = !LB1_PORT3_SFR[0] & (HC1_DAT[0] # QB1L169 # !QB1_TSEND);


--E1_B[0] is REG4:inst13|B[0]
E1_B[0] = DFFEAS(E1L3, LB1_OD[7],  ,  ,  ,  ,  ,  ,  );


--E1_B[1] is REG4:inst13|B[1]
E1_B[1] = DFFEAS(E1L5, LB1_OD[7],  ,  ,  ,  ,  ,  ,  );


--E1_B[2] is REG4:inst13|B[2]
E1_B[2] = DFFEAS(E1L7, LB1_OD[7],  ,  ,  ,  ,  ,  ,  );


--E1_B[3] is REG4:inst13|B[3]
E1_B[3] = DFFEAS(E1L9, LB1_OD[7],  ,  ,  ,  ,  ,  ,  );


--L1L7 is DECL7S:inst21|LED7S[6]~191
L1L7 = E1_B[0] & (E1_B[3] # E1_B[1] $ E1_B[2]) # !E1_B[0] & (E1_B[1] # E1_B[2] $ E1_B[3]);


--L1L6 is DECL7S:inst21|LED7S[5]~192
L1L6 = E1_B[0] & (E1_B[3] $ (E1_B[1] # !E1_B[2])) # !E1_B[0] & E1_B[1] & !E1_B[2] & !E1_B[3];


--L1L5 is DECL7S:inst21|LED7S[4]~193
L1L5 = E1_B[1] & E1_B[0] & (!E1_B[3]) # !E1_B[1] & (E1_B[2] & (!E1_B[3]) # !E1_B[2] & E1_B[0]);


--L1L4 is DECL7S:inst21|LED7S[3]~194
L1L4 = E1_B[1] & (E1_B[0] & E1_B[2] # !E1_B[0] & !E1_B[2] & E1_B[3]) # !E1_B[1] & !E1_B[3] & (E1_B[0] $ E1_B[2]);


--L1L3 is DECL7S:inst21|LED7S[2]~195
L1L3 = E1_B[2] & E1_B[3] & (E1_B[1] # !E1_B[0]) # !E1_B[2] & !E1_B[0] & E1_B[1] & !E1_B[3];


--L1L2 is DECL7S:inst21|LED7S[1]~196
L1L2 = E1_B[1] & (E1_B[0] & (E1_B[3]) # !E1_B[0] & E1_B[2]) # !E1_B[1] & E1_B[2] & (E1_B[0] $ E1_B[3]);


--L1L1 is DECL7S:inst21|LED7S[0]~197
L1L1 = E1_B[2] & !E1_B[1] & (E1_B[0] $ !E1_B[3]) # !E1_B[2] & E1_B[0] & (E1_B[1] $ !E1_B[3]);


--E2_B[3] is REG4:inst14|B[3]
E2_B[3] = DFFEAS(E1L9, LB1_OD[6],  ,  ,  ,  ,  ,  ,  );


--E2_B[2] is REG4:inst14|B[2]
E2_B[2] = DFFEAS(E1L7, LB1_OD[6],  ,  ,  ,  ,  ,  ,  );


--E2_B[1] is REG4:inst14|B[1]
E2_B[1] = DFFEAS(E1L5, LB1_OD[6],  ,  ,  ,  ,  ,  ,  );


--E2_B[0] is REG4:inst14|B[0]
E2_B[0] = DFFEAS(E1L3, LB1_OD[6],  ,  ,  ,  ,  ,  ,  );


--E3_B[3] is REG4:inst15|B[3]
E3_B[3] = DFFEAS(E1L9, !LB1_PORT3_SFR[5],  ,  ,  ,  ,  ,  ,  );


--E3_B[2] is REG4:inst15|B[2]
E3_B[2] = DFFEAS(E1L7, !LB1_PORT3_SFR[5],  ,  ,  ,  ,  ,  ,  );


--E3_B[1] is REG4:inst15|B[1]
E3_B[1] = DFFEAS(E1L5, !LB1_PORT3_SFR[5],  ,  ,  ,  ,  ,  ,  );


--E3_B[0] is REG4:inst15|B[0]
E3_B[0] = DFFEAS(E1L3, !LB1_PORT3_SFR[5],  ,  ,  ,  ,  ,  ,  );


--AB1_dffs[9] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[9]
AB1_dffs[9] = DFFEAS(AB1L50, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--AB1_dffs[6] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[6]
AB1_dffs[6] = DFFEAS(AB1L35, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--AB1_dffs[3] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[3]
AB1_dffs[3] = DFFEAS(AB1L20, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--Y1L1 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|XOR3:inst33|1~13
Y1L1 = AB1_dffs[9] $ AB1_dffs[6] $ AB1_dffs[3];


--B1_inst19 is CPU8051V1:inst|inst19
B1_inst19 = DFFEAS(B1L9, B1_inst9,  ,  ,  ,  ,  ,  ,  );


--R1_inst10 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst10
R1_inst10 = DFFEAS(VCC, X1_Equal0, !S1_inst,  ,  ,  ,  ,  ,  );


--R1_inst15 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst15
R1_inst15 = B1_inst19 & !R1_inst10;


--AB1_dffs[4] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[4]
AB1_dffs[4] = DFFEAS(AB1L25, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--AB1_dffs[8] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[8]
AB1_dffs[8] = DFFEAS(AB1L45, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--AB1_dffs[1] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]
AB1_dffs[1] = DFFEAS(AB1L10, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--Y2_1 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|XOR3:inst34|1
Y2_1 = AB1_dffs[4] $ AB1_dffs[8] $ AB1_dffs[1];


--AB1_dffs[23] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|RTYY:inst2|lpm_shiftreg:lpm_shiftreg_component|dffs[23]
AB1_dffs[23] = DFFEAS(AB1L120, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--A1L6 is altera_internal_jtag~TDO
A1L6 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , M1L20);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , M1L20);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , M1L20);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , M1L20);


--R1_inst5 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst5
R1_inst5 = DFFEAS(R1L4, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--R1_inst18 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst18
R1_inst18 = MT $ R1_inst5;


--R1_inst19 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst19
R1_inst19 = DFFEAS(R1L15, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--R1_inst20 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst20
R1_inst20 = R1_inst19 $ NO;


--R1_inst24 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst24
R1_inst24 = !R1_inst10 & !R1_inst18 & R1_inst15 & !R1_inst20;


--Z1_CQI[2] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[2]
Z1_CQI[2] = DFFEAS(Z1L16, R1_inst24, !R1L23,  ,  ,  ,  ,  ,  );


--Z1_CQI[0] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[0]
Z1_CQI[0] = DFFEAS(Z1L5, R1_inst24, !R1L23,  ,  ,  ,  ,  ,  );


--Z1_CQI[1] is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[1]
Z1_CQI[1] = DFFEAS(Z1L11, R1_inst24, !R1L23,  ,  ,  ,  ,  ,  );


--Z1L11 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[1]~ICOMBOUT
Z1L11 = Z1_CQI[0] & (Z1_CQI[1] $ VCC) # !Z1_CQI[0] & Z1_CQI[1] & VCC;

--Z1L9 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[1]~36
Z1L9 = CARRY(Z1_CQI[0] & Z1_CQI[1]);


--Z1L16 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[2]~ICOMBOUT
Z1L16 = Z1_CQI[2] & !Z1L9 # !Z1_CQI[2] & (Z1L9 # GND);

--Z1L14 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[2]~34
Z1L14 = CARRY(!Z1L9 # !Z1_CQI[2]);


--Z1L21 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3]~ICOMBOUT
Z1L21 = Z1_CQI[3] & (Z1L14 $ GND) # !Z1_CQI[3] & !Z1L14 & VCC;

--Z1L19 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[3]~28
Z1L19 = CARRY(Z1_CQI[3] & !Z1L14);


--Z1L26 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4]~ICOMBOUT
Z1L26 = Z1_CQI[4] & !Z1L19 # !Z1_CQI[4] & (Z1L19 # GND);

--Z1L24 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[4]~30
Z1L24 = CARRY(!Z1L19 # !Z1_CQI[4]);


--S1_inst is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|START:inst1|inst
S1_inst = DFFEAS(S1L9, S1_inst3, !RST,  ,  ,  ,  ,  ,  );


--R1_inst30 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst30
R1_inst30 = DFFEAS(R1_inst18, R1_inst15,  ,  ,  ,  ,  ,  ,  );


--R1L23 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|inst23~34
R1L23 = S1_inst # W1_Q # R1_inst30;


--Z1L30 is CPU8051V1:inst|JM_S1:inst|FPGA_1:inst1|CNT6C:inst35|CQI[5]~ICOMBOUT
Z1L30 = Z1_CQI[5] $ !Z1L24;


--UC1__clk0 is pll50:inst17|altpll:altpll_component|_clk0
UC1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLK), .INCLK());