spc.map.eqn

Alera 的8051 IP core的示例文件5个

V1_q_a[0]_PORT_B_data_in = W1_ram_rom_data_reg[0];
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = W1L3;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = F1L47;
V1_q_a[0]_clock_1 = A1L6;
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[0] = V1_q_a[0]_PORT_A_data_out[0];

--V1_q_b[0] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[0]
V1_q_b[0]_PORT_A_data_in = D1_DOUT[0];
V1_q_b[0]_PORT_A_data_in_reg = DFFE(V1_q_b[0]_PORT_A_data_in, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_data_in = W1_ram_rom_data_reg[0];
V1_q_b[0]_PORT_B_data_in_reg = DFFE(V1_q_b[0]_PORT_B_data_in, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[0]_PORT_A_address_reg = DFFE(V1_q_b[0]_PORT_A_address, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[0]_PORT_B_address_reg = DFFE(V1_q_b[0]_PORT_B_address, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[0]_PORT_A_write_enable_reg = DFFE(V1_q_b[0]_PORT_A_write_enable, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_write_enable = W1L3;
V1_q_b[0]_PORT_B_write_enable_reg = DFFE(V1_q_b[0]_PORT_B_write_enable, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_clock_0 = F1L47;
V1_q_b[0]_clock_1 = A1L6;
V1_q_b[0]_PORT_B_data_out = MEMORY(V1_q_b[0]_PORT_A_data_in_reg, V1_q_b[0]_PORT_B_data_in_reg, V1_q_b[0]_PORT_A_address_reg, V1_q_b[0]_PORT_B_address_reg, V1_q_b[0]_PORT_A_write_enable_reg, V1_q_b[0]_PORT_B_write_enable_reg, , , V1_q_b[0]_clock_0, V1_q_b[0]_clock_1, , , , );
V1_q_b[0] = V1_q_b[0]_PORT_B_data_out[0];


--V1_q_a[2] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[2]_PORT_A_data_in = D1_DOUT[2];
V1_q_a[2]_PORT_A_data_in_reg = DFFE(V1_q_a[2]_PORT_A_data_in, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_data_in = W1_ram_rom_data_reg[2];
V1_q_a[2]_PORT_B_data_in_reg = DFFE(V1_q_a[2]_PORT_B_data_in, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[2]_PORT_A_address_reg = DFFE(V1_q_a[2]_PORT_A_address, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[2]_PORT_B_address_reg = DFFE(V1_q_a[2]_PORT_B_address, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[2]_PORT_A_write_enable_reg = DFFE(V1_q_a[2]_PORT_A_write_enable, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_write_enable = W1L3;
V1_q_a[2]_PORT_B_write_enable_reg = DFFE(V1_q_a[2]_PORT_B_write_enable, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_clock_0 = F1L47;
V1_q_a[2]_clock_1 = A1L6;
V1_q_a[2]_PORT_A_data_out = MEMORY(V1_q_a[2]_PORT_A_data_in_reg, V1_q_a[2]_PORT_B_data_in_reg, V1_q_a[2]_PORT_A_address_reg, V1_q_a[2]_PORT_B_address_reg, V1_q_a[2]_PORT_A_write_enable_reg, V1_q_a[2]_PORT_B_write_enable_reg, , , V1_q_a[2]_clock_0, V1_q_a[2]_clock_1, , , , );
V1_q_a[2] = V1_q_a[2]_PORT_A_data_out[0];

--V1_q_b[2] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[2]
V1_q_b[2]_PORT_A_data_in = D1_DOUT[2];
V1_q_b[2]_PORT_A_data_in_reg = DFFE(V1_q_b[2]_PORT_A_data_in, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_data_in = W1_ram_rom_data_reg[2];
V1_q_b[2]_PORT_B_data_in_reg = DFFE(V1_q_b[2]_PORT_B_data_in, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[2]_PORT_A_address_reg = DFFE(V1_q_b[2]_PORT_A_address, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[2]_PORT_B_address_reg = DFFE(V1_q_b[2]_PORT_B_address, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[2]_PORT_A_write_enable_reg = DFFE(V1_q_b[2]_PORT_A_write_enable, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_write_enable = W1L3;
V1_q_b[2]_PORT_B_write_enable_reg = DFFE(V1_q_b[2]_PORT_B_write_enable, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_clock_0 = F1L47;
V1_q_b[2]_clock_1 = A1L6;
V1_q_b[2]_PORT_B_data_out = MEMORY(V1_q_b[2]_PORT_A_data_in_reg, V1_q_b[2]_PORT_B_data_in_reg, V1_q_b[2]_PORT_A_address_reg, V1_q_b[2]_PORT_B_address_reg, V1_q_b[2]_PORT_A_write_enable_reg, V1_q_b[2]_PORT_B_write_enable_reg, , , V1_q_b[2]_clock_0, V1_q_b[2]_clock_1, , , , );
V1_q_b[2] = V1_q_b[2]_PORT_B_data_out[0];


--V1_q_a[1] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[1]_PORT_A_data_in = D1_DOUT[1];
V1_q_a[1]_PORT_A_data_in_reg = DFFE(V1_q_a[1]_PORT_A_data_in, V1_q_a[1]_clock_0, , , );
V1_q_a[1]_PORT_B_data_in = W1_ram_rom_data_reg[1];
V1_q_a[1]_PORT_B_data_in_reg = DFFE(V1_q_a[1]_PORT_B_data_in, V1_q_a[1]_clock_1, , , );
V1_q_a[1]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[1]_PORT_A_address_reg = DFFE(V1_q_a[1]_PORT_A_address, V1_q_a[1]_clock_0, , , );
V1_q_a[1]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[1]_PORT_B_address_reg = DFFE(V1_q_a[1]_PORT_B_address, V1_q_a[1]_clock_1, , , );
V1_q_a[1]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[1]_PORT_A_write_enable_reg = DFFE(V1_q_a[1]_PORT_A_write_enable, V1_q_a[1]_clock_0, , , );
V1_q_a[1]_PORT_B_write_enable = W1L3;
V1_q_a[1]_PORT_B_write_enable_reg = DFFE(V1_q_a[1]_PORT_B_write_enable, V1_q_a[1]_clock_1, , , );
V1_q_a[1]_clock_0 = F1L47;
V1_q_a[1]_clock_1 = A1L6;
V1_q_a[1]_PORT_A_data_out = MEMORY(V1_q_a[1]_PORT_A_data_in_reg, V1_q_a[1]_PORT_B_data_in_reg, V1_q_a[1]_PORT_A_address_reg, V1_q_a[1]_PORT_B_address_reg, V1_q_a[1]_PORT_A_write_enable_reg, V1_q_a[1]_PORT_B_write_enable_reg, , , V1_q_a[1]_clock_0, V1_q_a[1]_clock_1, , , , );
V1_q_a[1] = V1_q_a[1]_PORT_A_data_out[0];

--V1_q_b[1] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[1]
V1_q_b[1]_PORT_A_data_in = D1_DOUT[1];
V1_q_b[1]_PORT_A_data_in_reg = DFFE(V1_q_b[1]_PORT_A_data_in, V1_q_b[1]_clock_0, , , );
V1_q_b[1]_PORT_B_data_in = W1_ram_rom_data_reg[1];
V1_q_b[1]_PORT_B_data_in_reg = DFFE(V1_q_b[1]_PORT_B_data_in, V1_q_b[1]_clock_1, , , );
V1_q_b[1]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[1]_PORT_A_address_reg = DFFE(V1_q_b[1]_PORT_A_address, V1_q_b[1]_clock_0, , , );
V1_q_b[1]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[1]_PORT_B_address_reg = DFFE(V1_q_b[1]_PORT_B_address, V1_q_b[1]_clock_1, , , );
V1_q_b[1]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[1]_PORT_A_write_enable_reg = DFFE(V1_q_b[1]_PORT_A_write_enable, V1_q_b[1]_clock_0, , , );
V1_q_b[1]_PORT_B_write_enable = W1L3;
V1_q_b[1]_PORT_B_write_enable_reg = DFFE(V1_q_b[1]_PORT_B_write_enable, V1_q_b[1]_clock_1, , , );
V1_q_b[1]_clock_0 = F1L47;
V1_q_b[1]_clock_1 = A1L6;
V1_q_b[1]_PORT_B_data_out = MEMORY(V1_q_b[1]_PORT_A_data_in_reg, V1_q_b[1]_PORT_B_data_in_reg, V1_q_b[1]_PORT_A_address_reg, V1_q_b[1]_PORT_B_address_reg, V1_q_b[1]_PORT_A_write_enable_reg, V1_q_b[1]_PORT_B_write_enable_reg, , , V1_q_b[1]_clock_0, V1_q_b[1]_clock_1, , , , );
V1_q_b[1] = V1_q_b[1]_PORT_B_data_out[0];


--N1L21 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|Select~709
N1L21 = V1_q_a[2] & (V1_q_a[1] & V1_q_a[6] # !V1_q_a[0]) # !V1_q_a[2] & !V1_q_a[0] & (V1_q_a[1] # V1_q_a[6]);


--N1L22 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|Select~710
N1L22 = V1_q_a[7] & (N1L20 & N1L21 # !V1_q_a[0]) # !V1_q_a[7] & !V1_q_a[0] & (N1L20 # N1L21);


--N1L23 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|Select~711
N1L23 = N1_state.f_end_s # N1_state.f_ready_s & !N1L22;


--R1_xmit_done is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xmit_done
R1_xmit_done = DFFEAS(R1L1, Q1L40, RST,  ,  ,  ,  ,  ,  );


--N1_framecnt[9] is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|framecnt[9]
N1_framecnt[9] = DFFEAS(N1L142, N1L92, !N1L192,  ,  ,  ,  , N1_framecnt[9],  );


--N1L228 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|xdata[2]~20
N1L228 = N1_state.f_ready_s & R1_xmit_done & !N1_framecnt[9];


--N1_state.f_start_s is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|state.f_start_s
N1_state.f_start_s = DFFEAS(N1_next_state.f_start_s, Q1L40, RST,  ,  ,  ,  ,  ,  );


--N1L229 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|xdata[2]~79
N1L229 = N1L228 # !N1_state.f_ready_s & (N1_state.f_end_s # N1_state.f_start_s);


--R1L36 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|partoser~396
R1L36 = R1_xmit_cmd_p & !R1_state.x_idle;


--R1L4 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|next_state.x_start~30~64
R1L4 = R1L36 # R1_state.x_start & (!B1L7 # !R1_xcnt16[0]);


--CB10_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2]
CB10_Q[2] = AMPP_FUNCTION(A1L6, A1L20, L1_CLRN_SIGNAL, L1L43);


--FB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
FB1_state[3] = AMPP_FUNCTION(A1L6, FB1L19);


--FB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
FB1_state[4] = AMPP_FUNCTION(A1L6, FB1L20, A1L8);


--L1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
L1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L6, A1L17, FB1_state[0], FB1_state[12]);


--W1L11 is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33
W1L11 = AMPP_FUNCTION(FB1_state[3], FB1_state[4], L1_jtag_debug_mode_usr1);


--X3_WORD_SR[0] is ROM3:inst14|altsyncram:altsyncram_component|altsyncram_uk61:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0]
X3_WORD_SR[0] = AMPP_FUNCTION(A1L6, X3L27, X3L23);


--CB4_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[1]
CB4_Q[1] = AMPP_FUNCTION(A1L6, L1L39, L1_CLRN_SIGNAL, L1L47);


--CB4_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2]
CB4_Q[2] = AMPP_FUNCTION(A1L6, L1L40, L1_CLRN_SIGNAL, L1L47);


--CB4L5 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2]~61
CB4L5 = AMPP_FUNCTION(CB4_Q[1], CB4_Q[2]);


--W3_bypass_reg_out is ROM3:inst14|altsyncram:altsyncram_component|altsyncram_uk61:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out
W3_bypass_reg_out = AMPP_FUNCTION(A1L6, W3L2, L1_CLRN_SIGNAL);


--CB4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[0]
CB4_Q[0] = AMPP_FUNCTION(A1L6, L1L38, L1_CLRN_SIGNAL, L1L47);


--L1L14 is sld_hub:sld_hub_inst|hub_tdo~1167
L1L14 = AMPP_FUNCTION(X3_WORD_SR[0], CB4L5, W3_bypass_reg_out, CB4_Q[0]);


--W3_ram_rom_data_reg[0] is ROM3:inst14|altsyncram:altsyncram_component|altsyncram_uk61:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
W3_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L6, W3L51, W3L50);


--L1L15 is sld_hub:sld_hub_inst|hub_tdo~1168
L1L15 = AMPP_FUNCTION(W3_ram_rom_data_reg[0], CB4_Q[1], CB4_Q[2], CB4_Q[0]);


--L1L16 is sld_hub:sld_hub_inst|hub_tdo~1169
L1L16 = AMPP_FUNCTION(CB10_Q[2], W1L11, L1L14, L1L15);


--CB10_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1]
CB10_Q[1] = AMPP_FUNCTION(A1L6, A1L19, L1_CLRN_SIGNAL, L1L43);


--X2_WORD_SR[0] is ROMH:inst11|altsyncram:altsyncram_component|altsyncram_bj61:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0]
X2_WORD_SR[0] = AMPP_FUNCTION(A1L6, X2L25, X2L23);


--CB5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[1]
CB5_Q[1] = AMPP_FUNCTION(A1L6, L1L34, L1_CLRN_SIGNAL, L1L46);


--CB5_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[2]
CB5_Q[2] = AMPP_FUNCTION(A1L6, L1L35, L1_CLRN_SIGNAL, L1L46);


--CB5L5 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[2]~61
CB5L5 = AMPP_FUNCTION(CB5_Q[1], CB5_Q[2]);


--W2_bypass_reg_out is ROMH:inst11|altsyncram:altsyncram_component|altsyncram_bj61:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out
W2_bypass_reg_out = AMPP_FUNCTION(A1L6, W2L2, L1_CLRN_SIGNAL);


--CB5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]
CB5_Q[0] = AMPP_FUNCTION(A1L6, L1L33, L1_CLRN_SIGNAL, L1L46);


--L1L17 is sld_hub:sld_hub_inst|hub_tdo~1170