spc.map.eqn

Alera 的8051 IP core的示例文件5个

--R1L2 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|next_state.x_idle~35~0
R1L2 = !R1_state.x_idle & !R1_xmit_cmd_p;


--Q1_bclk_t is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_baud:iBAUD|bclk_t
Q1_bclk_t = DFFEAS(Q1L35, B1L4, RST,  ,  ,  ,  ,  ,  );


--R1_partoser[2] is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|partoser[2]
R1_partoser[2] = DFFEAS(R1L31, Q1L40, RST,  , R1L17,  ,  ,  ,  );


--N1_xdata[1] is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|xdata[1]
N1_xdata[1] = DFFEAS(N1L7, Q1L40,  ,  , N1L229,  ,  ,  ,  );


--R1L30 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|partoser~36
R1L30 = R1_xmit_cmd_p & (R1_state.x_idle & R1_partoser[2] # !R1_state.x_idle & (N1_xdata[1])) # !R1_xmit_cmd_p & R1_partoser[2];


--N1_state.f_end_s is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|state.f_end_s
N1_state.f_end_s = DFFEAS(N1_next_state.f_end_s, Q1L40, RST,  ,  ,  ,  ,  ,  );


--N1_state.f_ready_s is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|state.f_ready_s
N1_state.f_ready_s = DFFEAS(N1_next_state.f_ready_s, Q1L40, RST,  ,  ,  ,  ,  ,  );


--V1_q_a[7] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[7]_PORT_A_data_in = D1_DOUT[7];
V1_q_a[7]_PORT_A_data_in_reg = DFFE(V1_q_a[7]_PORT_A_data_in, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_PORT_B_data_in = W1_ram_rom_data_reg[7];
V1_q_a[7]_PORT_B_data_in_reg = DFFE(V1_q_a[7]_PORT_B_data_in, V1_q_a[7]_clock_1, , , );
V1_q_a[7]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[7]_PORT_A_address_reg = DFFE(V1_q_a[7]_PORT_A_address, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[7]_PORT_B_address_reg = DFFE(V1_q_a[7]_PORT_B_address, V1_q_a[7]_clock_1, , , );
V1_q_a[7]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[7]_PORT_A_write_enable_reg = DFFE(V1_q_a[7]_PORT_A_write_enable, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_PORT_B_write_enable = W1L3;
V1_q_a[7]_PORT_B_write_enable_reg = DFFE(V1_q_a[7]_PORT_B_write_enable, V1_q_a[7]_clock_1, , , );
V1_q_a[7]_clock_0 = F1L47;
V1_q_a[7]_clock_1 = A1L6;
V1_q_a[7]_PORT_A_data_out = MEMORY(V1_q_a[7]_PORT_A_data_in_reg, V1_q_a[7]_PORT_B_data_in_reg, V1_q_a[7]_PORT_A_address_reg, V1_q_a[7]_PORT_B_address_reg, V1_q_a[7]_PORT_A_write_enable_reg, V1_q_a[7]_PORT_B_write_enable_reg, , , V1_q_a[7]_clock_0, V1_q_a[7]_clock_1, , , , );
V1_q_a[7] = V1_q_a[7]_PORT_A_data_out[0];

--V1_q_b[7] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[7]
V1_q_b[7]_PORT_A_data_in = D1_DOUT[7];
V1_q_b[7]_PORT_A_data_in_reg = DFFE(V1_q_b[7]_PORT_A_data_in, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_data_in = W1_ram_rom_data_reg[7];
V1_q_b[7]_PORT_B_data_in_reg = DFFE(V1_q_b[7]_PORT_B_data_in, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[7]_PORT_A_address_reg = DFFE(V1_q_b[7]_PORT_A_address, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[7]_PORT_B_address_reg = DFFE(V1_q_b[7]_PORT_B_address, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[7]_PORT_A_write_enable_reg = DFFE(V1_q_b[7]_PORT_A_write_enable, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_write_enable = W1L3;
V1_q_b[7]_PORT_B_write_enable_reg = DFFE(V1_q_b[7]_PORT_B_write_enable, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_clock_0 = F1L47;
V1_q_b[7]_clock_1 = A1L6;
V1_q_b[7]_PORT_B_data_out = MEMORY(V1_q_b[7]_PORT_A_data_in_reg, V1_q_b[7]_PORT_B_data_in_reg, V1_q_b[7]_PORT_A_address_reg, V1_q_b[7]_PORT_B_address_reg, V1_q_b[7]_PORT_A_write_enable_reg, V1_q_b[7]_PORT_B_write_enable_reg, , , V1_q_b[7]_clock_0, V1_q_b[7]_clock_1, , , , );
V1_q_b[7] = V1_q_b[7]_PORT_B_data_out[0];


--V1_q_a[6] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[6]_PORT_A_data_in = D1_DOUT[6];
V1_q_a[6]_PORT_A_data_in_reg = DFFE(V1_q_a[6]_PORT_A_data_in, V1_q_a[6]_clock_0, , , );
V1_q_a[6]_PORT_B_data_in = W1_ram_rom_data_reg[6];
V1_q_a[6]_PORT_B_data_in_reg = DFFE(V1_q_a[6]_PORT_B_data_in, V1_q_a[6]_clock_1, , , );
V1_q_a[6]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[6]_PORT_A_address_reg = DFFE(V1_q_a[6]_PORT_A_address, V1_q_a[6]_clock_0, , , );
V1_q_a[6]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[6]_PORT_B_address_reg = DFFE(V1_q_a[6]_PORT_B_address, V1_q_a[6]_clock_1, , , );
V1_q_a[6]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[6]_PORT_A_write_enable_reg = DFFE(V1_q_a[6]_PORT_A_write_enable, V1_q_a[6]_clock_0, , , );
V1_q_a[6]_PORT_B_write_enable = W1L3;
V1_q_a[6]_PORT_B_write_enable_reg = DFFE(V1_q_a[6]_PORT_B_write_enable, V1_q_a[6]_clock_1, , , );
V1_q_a[6]_clock_0 = F1L47;
V1_q_a[6]_clock_1 = A1L6;
V1_q_a[6]_PORT_A_data_out = MEMORY(V1_q_a[6]_PORT_A_data_in_reg, V1_q_a[6]_PORT_B_data_in_reg, V1_q_a[6]_PORT_A_address_reg, V1_q_a[6]_PORT_B_address_reg, V1_q_a[6]_PORT_A_write_enable_reg, V1_q_a[6]_PORT_B_write_enable_reg, , , V1_q_a[6]_clock_0, V1_q_a[6]_clock_1, , , , );
V1_q_a[6] = V1_q_a[6]_PORT_A_data_out[0];

--V1_q_b[6] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[6]
V1_q_b[6]_PORT_A_data_in = D1_DOUT[6];
V1_q_b[6]_PORT_A_data_in_reg = DFFE(V1_q_b[6]_PORT_A_data_in, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_data_in = W1_ram_rom_data_reg[6];
V1_q_b[6]_PORT_B_data_in_reg = DFFE(V1_q_b[6]_PORT_B_data_in, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[6]_PORT_A_address_reg = DFFE(V1_q_b[6]_PORT_A_address, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[6]_PORT_B_address_reg = DFFE(V1_q_b[6]_PORT_B_address, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[6]_PORT_A_write_enable_reg = DFFE(V1_q_b[6]_PORT_A_write_enable, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_write_enable = W1L3;
V1_q_b[6]_PORT_B_write_enable_reg = DFFE(V1_q_b[6]_PORT_B_write_enable, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_clock_0 = F1L47;
V1_q_b[6]_clock_1 = A1L6;
V1_q_b[6]_PORT_B_data_out = MEMORY(V1_q_b[6]_PORT_A_data_in_reg, V1_q_b[6]_PORT_B_data_in_reg, V1_q_b[6]_PORT_A_address_reg, V1_q_b[6]_PORT_B_address_reg, V1_q_b[6]_PORT_A_write_enable_reg, V1_q_b[6]_PORT_B_write_enable_reg, , , V1_q_b[6]_clock_0, V1_q_b[6]_clock_1, , , , );
V1_q_b[6] = V1_q_b[6]_PORT_B_data_out[0];


--V1_q_a[4] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[4]_PORT_A_data_in = D1_DOUT[4];
V1_q_a[4]_PORT_A_data_in_reg = DFFE(V1_q_a[4]_PORT_A_data_in, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_PORT_B_data_in = W1_ram_rom_data_reg[4];
V1_q_a[4]_PORT_B_data_in_reg = DFFE(V1_q_a[4]_PORT_B_data_in, V1_q_a[4]_clock_1, , , );
V1_q_a[4]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[4]_PORT_B_address_reg = DFFE(V1_q_a[4]_PORT_B_address, V1_q_a[4]_clock_1, , , );
V1_q_a[4]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[4]_PORT_A_write_enable_reg = DFFE(V1_q_a[4]_PORT_A_write_enable, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_PORT_B_write_enable = W1L3;
V1_q_a[4]_PORT_B_write_enable_reg = DFFE(V1_q_a[4]_PORT_B_write_enable, V1_q_a[4]_clock_1, , , );
V1_q_a[4]_clock_0 = F1L47;
V1_q_a[4]_clock_1 = A1L6;
V1_q_a[4]_PORT_A_data_out = MEMORY(V1_q_a[4]_PORT_A_data_in_reg, V1_q_a[4]_PORT_B_data_in_reg, V1_q_a[4]_PORT_A_address_reg, V1_q_a[4]_PORT_B_address_reg, V1_q_a[4]_PORT_A_write_enable_reg, V1_q_a[4]_PORT_B_write_enable_reg, , , V1_q_a[4]_clock_0, V1_q_a[4]_clock_1, , , , );
V1_q_a[4] = V1_q_a[4]_PORT_A_data_out[0];

--V1_q_b[4] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[4]
V1_q_b[4]_PORT_A_data_in = D1_DOUT[4];
V1_q_b[4]_PORT_A_data_in_reg = DFFE(V1_q_b[4]_PORT_A_data_in, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_data_in = W1_ram_rom_data_reg[4];
V1_q_b[4]_PORT_B_data_in_reg = DFFE(V1_q_b[4]_PORT_B_data_in, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[4]_PORT_A_address_reg = DFFE(V1_q_b[4]_PORT_A_address, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[4]_PORT_B_address_reg = DFFE(V1_q_b[4]_PORT_B_address, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[4]_PORT_A_write_enable_reg = DFFE(V1_q_b[4]_PORT_A_write_enable, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_write_enable = W1L3;
V1_q_b[4]_PORT_B_write_enable_reg = DFFE(V1_q_b[4]_PORT_B_write_enable, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_clock_0 = F1L47;
V1_q_b[4]_clock_1 = A1L6;
V1_q_b[4]_PORT_B_data_out = MEMORY(V1_q_b[4]_PORT_A_data_in_reg, V1_q_b[4]_PORT_B_data_in_reg, V1_q_b[4]_PORT_A_address_reg, V1_q_b[4]_PORT_B_address_reg, V1_q_b[4]_PORT_A_write_enable_reg, V1_q_b[4]_PORT_B_write_enable_reg, , , V1_q_b[4]_clock_0, V1_q_b[4]_clock_1, , , , );
V1_q_b[4] = V1_q_b[4]_PORT_B_data_out[0];


--V1_q_a[3] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[3]_PORT_A_data_in = D1_DOUT[3];
V1_q_a[3]_PORT_A_data_in_reg = DFFE(V1_q_a[3]_PORT_A_data_in, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_PORT_B_data_in = W1_ram_rom_data_reg[3];
V1_q_a[3]_PORT_B_data_in_reg = DFFE(V1_q_a[3]_PORT_B_data_in, V1_q_a[3]_clock_1, , , );
V1_q_a[3]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[3]_PORT_A_address_reg = DFFE(V1_q_a[3]_PORT_A_address, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[3]_PORT_B_address_reg = DFFE(V1_q_a[3]_PORT_B_address, V1_q_a[3]_clock_1, , , );
V1_q_a[3]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[3]_PORT_A_write_enable_reg = DFFE(V1_q_a[3]_PORT_A_write_enable, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_PORT_B_write_enable = W1L3;
V1_q_a[3]_PORT_B_write_enable_reg = DFFE(V1_q_a[3]_PORT_B_write_enable, V1_q_a[3]_clock_1, , , );
V1_q_a[3]_clock_0 = F1L47;
V1_q_a[3]_clock_1 = A1L6;
V1_q_a[3]_PORT_A_data_out = MEMORY(V1_q_a[3]_PORT_A_data_in_reg, V1_q_a[3]_PORT_B_data_in_reg, V1_q_a[3]_PORT_A_address_reg, V1_q_a[3]_PORT_B_address_reg, V1_q_a[3]_PORT_A_write_enable_reg, V1_q_a[3]_PORT_B_write_enable_reg, , , V1_q_a[3]_clock_0, V1_q_a[3]_clock_1, , , , );
V1_q_a[3] = V1_q_a[3]_PORT_A_data_out[0];

--V1_q_b[3] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[3]
V1_q_b[3]_PORT_A_data_in = D1_DOUT[3];
V1_q_b[3]_PORT_A_data_in_reg = DFFE(V1_q_b[3]_PORT_A_data_in, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_data_in = W1_ram_rom_data_reg[3];
V1_q_b[3]_PORT_B_data_in_reg = DFFE(V1_q_b[3]_PORT_B_data_in, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[3]_PORT_A_address_reg = DFFE(V1_q_b[3]_PORT_A_address, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[3]_PORT_B_address_reg = DFFE(V1_q_b[3]_PORT_B_address, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[3]_PORT_A_write_enable_reg = DFFE(V1_q_b[3]_PORT_A_write_enable, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_write_enable = W1L3;
V1_q_b[3]_PORT_B_write_enable_reg = DFFE(V1_q_b[3]_PORT_B_write_enable, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_clock_0 = F1L47;
V1_q_b[3]_clock_1 = A1L6;
V1_q_b[3]_PORT_B_data_out = MEMORY(V1_q_b[3]_PORT_A_data_in_reg, V1_q_b[3]_PORT_B_data_in_reg, V1_q_b[3]_PORT_A_address_reg, V1_q_b[3]_PORT_B_address_reg, V1_q_b[3]_PORT_A_write_enable_reg, V1_q_b[3]_PORT_B_write_enable_reg, , , V1_q_b[3]_clock_0, V1_q_b[3]_clock_1, , , , );
V1_q_b[3] = V1_q_b[3]_PORT_B_data_out[0];


--V1_q_a[5] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[5]_PORT_A_data_in = D1_DOUT[5];
V1_q_a[5]_PORT_A_data_in_reg = DFFE(V1_q_a[5]_PORT_A_data_in, V1_q_a[5]_clock_0, , , );
V1_q_a[5]_PORT_B_data_in = W1_ram_rom_data_reg[5];
V1_q_a[5]_PORT_B_data_in_reg = DFFE(V1_q_a[5]_PORT_B_data_in, V1_q_a[5]_clock_1, , , );
V1_q_a[5]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[5]_PORT_A_address_reg = DFFE(V1_q_a[5]_PORT_A_address, V1_q_a[5]_clock_0, , , );
V1_q_a[5]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[5]_PORT_B_address_reg = DFFE(V1_q_a[5]_PORT_B_address, V1_q_a[5]_clock_1, , , );
V1_q_a[5]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[5]_PORT_A_write_enable_reg = DFFE(V1_q_a[5]_PORT_A_write_enable, V1_q_a[5]_clock_0, , , );
V1_q_a[5]_PORT_B_write_enable = W1L3;
V1_q_a[5]_PORT_B_write_enable_reg = DFFE(V1_q_a[5]_PORT_B_write_enable, V1_q_a[5]_clock_1, , , );
V1_q_a[5]_clock_0 = F1L47;
V1_q_a[5]_clock_1 = A1L6;
V1_q_a[5]_PORT_A_data_out = MEMORY(V1_q_a[5]_PORT_A_data_in_reg, V1_q_a[5]_PORT_B_data_in_reg, V1_q_a[5]_PORT_A_address_reg, V1_q_a[5]_PORT_B_address_reg, V1_q_a[5]_PORT_A_write_enable_reg, V1_q_a[5]_PORT_B_write_enable_reg, , , V1_q_a[5]_clock_0, V1_q_a[5]_clock_1, , , , );
V1_q_a[5] = V1_q_a[5]_PORT_A_data_out[0];

--V1_q_b[5] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[5]
V1_q_b[5]_PORT_A_data_in = D1_DOUT[5];
V1_q_b[5]_PORT_A_data_in_reg = DFFE(V1_q_b[5]_PORT_A_data_in, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_B_data_in = W1_ram_rom_data_reg[5];
V1_q_b[5]_PORT_B_data_in_reg = DFFE(V1_q_b[5]_PORT_B_data_in, V1_q_b[5]_clock_1, , , );
V1_q_b[5]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[5]_PORT_A_address_reg = DFFE(V1_q_b[5]_PORT_A_address, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[5]_PORT_B_address_reg = DFFE(V1_q_b[5]_PORT_B_address, V1_q_b[5]_clock_1, , , );
V1_q_b[5]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[5]_PORT_A_write_enable_reg = DFFE(V1_q_b[5]_PORT_A_write_enable, V1_q_b[5]_clock_0, , , );
V1_q_b[5]_PORT_B_write_enable = W1L3;
V1_q_b[5]_PORT_B_write_enable_reg = DFFE(V1_q_b[5]_PORT_B_write_enable, V1_q_b[5]_clock_1, , , );
V1_q_b[5]_clock_0 = F1L47;
V1_q_b[5]_clock_1 = A1L6;
V1_q_b[5]_PORT_B_data_out = MEMORY(V1_q_b[5]_PORT_A_data_in_reg, V1_q_b[5]_PORT_B_data_in_reg, V1_q_b[5]_PORT_A_address_reg, V1_q_b[5]_PORT_B_address_reg, V1_q_b[5]_PORT_A_write_enable_reg, V1_q_b[5]_PORT_B_write_enable_reg, , , V1_q_b[5]_clock_0, V1_q_b[5]_clock_1, , , , );
V1_q_b[5] = V1_q_b[5]_PORT_B_data_out[0];


--N1L20 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|Select~708
N1L20 = V1_q_a[6] & V1_q_a[4] & V1_q_a[3] & V1_q_a[5] # !V1_q_a[6] & (V1_q_a[4] # V1_q_a[3] # V1_q_a[5]);


--V1_q_a[0] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[0]_PORT_A_data_in = D1_DOUT[0];
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );