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V1_q_a[2]_PORT_A_data_in = BUS(D1_DOUT[2], D1_DOUT[3], D1_DOUT[4], D1_DOUT[7]);
V1_q_a[2]_PORT_A_data_in_reg = DFFE(V1_q_a[2]_PORT_A_data_in, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[2], W1_ram_rom_data_reg[3], W1_ram_rom_data_reg[4], W1_ram_rom_data_reg[7]);
V1_q_a[2]_PORT_B_data_in_reg = DFFE(V1_q_a[2]_PORT_B_data_in, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[2]_PORT_A_address_reg = DFFE(V1_q_a[2]_PORT_A_address, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[2]_PORT_B_address_reg = DFFE(V1_q_a[2]_PORT_B_address, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[2]_PORT_A_write_enable_reg = DFFE(V1_q_a[2]_PORT_A_write_enable, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_write_enable = W1L3;
V1_q_a[2]_PORT_B_write_enable_reg = DFFE(V1_q_a[2]_PORT_B_write_enable, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_clock_0 = GLOBAL(F1L55);
V1_q_a[2]_clock_1 = GLOBAL(A1L8);
V1_q_a[2]_PORT_A_data_out = MEMORY(V1_q_a[2]_PORT_A_data_in_reg, V1_q_a[2]_PORT_B_data_in_reg, V1_q_a[2]_PORT_A_address_reg, V1_q_a[2]_PORT_B_address_reg, V1_q_a[2]_PORT_A_write_enable_reg, V1_q_a[2]_PORT_B_write_enable_reg, , , V1_q_a[2]_clock_0, V1_q_a[2]_clock_1, , , , );
V1_q_a[2] = V1_q_a[2]_PORT_A_data_out[0];
--V1_q_b[2] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[2] at M4K_X11_Y7
V1_q_b[2]_PORT_A_data_in = BUS(D1_DOUT[2], D1_DOUT[3], D1_DOUT[4], D1_DOUT[7]);
V1_q_b[2]_PORT_A_data_in_reg = DFFE(V1_q_b[2]_PORT_A_data_in, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[2], W1_ram_rom_data_reg[3], W1_ram_rom_data_reg[4], W1_ram_rom_data_reg[7]);
V1_q_b[2]_PORT_B_data_in_reg = DFFE(V1_q_b[2]_PORT_B_data_in, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[2]_PORT_A_address_reg = DFFE(V1_q_b[2]_PORT_A_address, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[2]_PORT_B_address_reg = DFFE(V1_q_b[2]_PORT_B_address, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[2]_PORT_A_write_enable_reg = DFFE(V1_q_b[2]_PORT_A_write_enable, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_write_enable = W1L3;
V1_q_b[2]_PORT_B_write_enable_reg = DFFE(V1_q_b[2]_PORT_B_write_enable, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_clock_0 = GLOBAL(F1L55);
V1_q_b[2]_clock_1 = GLOBAL(A1L8);
V1_q_b[2]_PORT_B_data_out = MEMORY(V1_q_b[2]_PORT_A_data_in_reg, V1_q_b[2]_PORT_B_data_in_reg, V1_q_b[2]_PORT_A_address_reg, V1_q_b[2]_PORT_B_address_reg, V1_q_b[2]_PORT_A_write_enable_reg, V1_q_b[2]_PORT_B_write_enable_reg, , , V1_q_b[2]_clock_0, V1_q_b[2]_clock_1, , , , );
V1_q_b[2] = V1_q_b[2]_PORT_B_data_out[0];
--V1_q_a[7] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[7] at M4K_X11_Y7
V1_q_a[2]_PORT_A_data_in = BUS(D1_DOUT[2], D1_DOUT[3], D1_DOUT[4], D1_DOUT[7]);
V1_q_a[2]_PORT_A_data_in_reg = DFFE(V1_q_a[2]_PORT_A_data_in, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[2], W1_ram_rom_data_reg[3], W1_ram_rom_data_reg[4], W1_ram_rom_data_reg[7]);
V1_q_a[2]_PORT_B_data_in_reg = DFFE(V1_q_a[2]_PORT_B_data_in, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[2]_PORT_A_address_reg = DFFE(V1_q_a[2]_PORT_A_address, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[2]_PORT_B_address_reg = DFFE(V1_q_a[2]_PORT_B_address, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[2]_PORT_A_write_enable_reg = DFFE(V1_q_a[2]_PORT_A_write_enable, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_write_enable = W1L3;
V1_q_a[2]_PORT_B_write_enable_reg = DFFE(V1_q_a[2]_PORT_B_write_enable, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_clock_0 = GLOBAL(F1L55);
V1_q_a[2]_clock_1 = GLOBAL(A1L8);
V1_q_a[2]_PORT_A_data_out = MEMORY(V1_q_a[2]_PORT_A_data_in_reg, V1_q_a[2]_PORT_B_data_in_reg, V1_q_a[2]_PORT_A_address_reg, V1_q_a[2]_PORT_B_address_reg, V1_q_a[2]_PORT_A_write_enable_reg, V1_q_a[2]_PORT_B_write_enable_reg, , , V1_q_a[2]_clock_0, V1_q_a[2]_clock_1, , , , );
V1_q_a[7] = V1_q_a[2]_PORT_A_data_out[3];
--V1_q_a[4] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[4] at M4K_X11_Y7
V1_q_a[2]_PORT_A_data_in = BUS(D1_DOUT[2], D1_DOUT[3], D1_DOUT[4], D1_DOUT[7]);
V1_q_a[2]_PORT_A_data_in_reg = DFFE(V1_q_a[2]_PORT_A_data_in, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[2], W1_ram_rom_data_reg[3], W1_ram_rom_data_reg[4], W1_ram_rom_data_reg[7]);
V1_q_a[2]_PORT_B_data_in_reg = DFFE(V1_q_a[2]_PORT_B_data_in, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[2]_PORT_A_address_reg = DFFE(V1_q_a[2]_PORT_A_address, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[2]_PORT_B_address_reg = DFFE(V1_q_a[2]_PORT_B_address, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[2]_PORT_A_write_enable_reg = DFFE(V1_q_a[2]_PORT_A_write_enable, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_write_enable = W1L3;
V1_q_a[2]_PORT_B_write_enable_reg = DFFE(V1_q_a[2]_PORT_B_write_enable, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_clock_0 = GLOBAL(F1L55);
V1_q_a[2]_clock_1 = GLOBAL(A1L8);
V1_q_a[2]_PORT_A_data_out = MEMORY(V1_q_a[2]_PORT_A_data_in_reg, V1_q_a[2]_PORT_B_data_in_reg, V1_q_a[2]_PORT_A_address_reg, V1_q_a[2]_PORT_B_address_reg, V1_q_a[2]_PORT_A_write_enable_reg, V1_q_a[2]_PORT_B_write_enable_reg, , , V1_q_a[2]_clock_0, V1_q_a[2]_clock_1, , , , );
V1_q_a[4] = V1_q_a[2]_PORT_A_data_out[2];
--V1_q_a[3] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[3] at M4K_X11_Y7
V1_q_a[2]_PORT_A_data_in = BUS(D1_DOUT[2], D1_DOUT[3], D1_DOUT[4], D1_DOUT[7]);
V1_q_a[2]_PORT_A_data_in_reg = DFFE(V1_q_a[2]_PORT_A_data_in, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[2], W1_ram_rom_data_reg[3], W1_ram_rom_data_reg[4], W1_ram_rom_data_reg[7]);
V1_q_a[2]_PORT_B_data_in_reg = DFFE(V1_q_a[2]_PORT_B_data_in, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[2]_PORT_A_address_reg = DFFE(V1_q_a[2]_PORT_A_address, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[2]_PORT_B_address_reg = DFFE(V1_q_a[2]_PORT_B_address, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[2]_PORT_A_write_enable_reg = DFFE(V1_q_a[2]_PORT_A_write_enable, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_PORT_B_write_enable = W1L3;
V1_q_a[2]_PORT_B_write_enable_reg = DFFE(V1_q_a[2]_PORT_B_write_enable, V1_q_a[2]_clock_1, , , );
V1_q_a[2]_clock_0 = GLOBAL(F1L55);
V1_q_a[2]_clock_1 = GLOBAL(A1L8);
V1_q_a[2]_PORT_A_data_out = MEMORY(V1_q_a[2]_PORT_A_data_in_reg, V1_q_a[2]_PORT_B_data_in_reg, V1_q_a[2]_PORT_A_address_reg, V1_q_a[2]_PORT_B_address_reg, V1_q_a[2]_PORT_A_write_enable_reg, V1_q_a[2]_PORT_B_write_enable_reg, , , V1_q_a[2]_clock_0, V1_q_a[2]_clock_1, , , , );
V1_q_a[3] = V1_q_a[2]_PORT_A_data_out[1];
--V1_q_b[7] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[7] at M4K_X11_Y7
V1_q_b[2]_PORT_A_data_in = BUS(D1_DOUT[2], D1_DOUT[3], D1_DOUT[4], D1_DOUT[7]);
V1_q_b[2]_PORT_A_data_in_reg = DFFE(V1_q_b[2]_PORT_A_data_in, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[2], W1_ram_rom_data_reg[3], W1_ram_rom_data_reg[4], W1_ram_rom_data_reg[7]);
V1_q_b[2]_PORT_B_data_in_reg = DFFE(V1_q_b[2]_PORT_B_data_in, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[2]_PORT_A_address_reg = DFFE(V1_q_b[2]_PORT_A_address, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[2]_PORT_B_address_reg = DFFE(V1_q_b[2]_PORT_B_address, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[2]_PORT_A_write_enable_reg = DFFE(V1_q_b[2]_PORT_A_write_enable, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_write_enable = W1L3;
V1_q_b[2]_PORT_B_write_enable_reg = DFFE(V1_q_b[2]_PORT_B_write_enable, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_clock_0 = GLOBAL(F1L55);
V1_q_b[2]_clock_1 = GLOBAL(A1L8);
V1_q_b[2]_PORT_B_data_out = MEMORY(V1_q_b[2]_PORT_A_data_in_reg, V1_q_b[2]_PORT_B_data_in_reg, V1_q_b[2]_PORT_A_address_reg, V1_q_b[2]_PORT_B_address_reg, V1_q_b[2]_PORT_A_write_enable_reg, V1_q_b[2]_PORT_B_write_enable_reg, , , V1_q_b[2]_clock_0, V1_q_b[2]_clock_1, , , , );
V1_q_b[7] = V1_q_b[2]_PORT_B_data_out[3];
--V1_q_b[4] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[4] at M4K_X11_Y7
V1_q_b[2]_PORT_A_data_in = BUS(D1_DOUT[2], D1_DOUT[3], D1_DOUT[4], D1_DOUT[7]);
V1_q_b[2]_PORT_A_data_in_reg = DFFE(V1_q_b[2]_PORT_A_data_in, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[2], W1_ram_rom_data_reg[3], W1_ram_rom_data_reg[4], W1_ram_rom_data_reg[7]);
V1_q_b[2]_PORT_B_data_in_reg = DFFE(V1_q_b[2]_PORT_B_data_in, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[2]_PORT_A_address_reg = DFFE(V1_q_b[2]_PORT_A_address, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[2]_PORT_B_address_reg = DFFE(V1_q_b[2]_PORT_B_address, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[2]_PORT_A_write_enable_reg = DFFE(V1_q_b[2]_PORT_A_write_enable, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_write_enable = W1L3;
V1_q_b[2]_PORT_B_write_enable_reg = DFFE(V1_q_b[2]_PORT_B_write_enable, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_clock_0 = GLOBAL(F1L55);
V1_q_b[2]_clock_1 = GLOBAL(A1L8);
V1_q_b[2]_PORT_B_data_out = MEMORY(V1_q_b[2]_PORT_A_data_in_reg, V1_q_b[2]_PORT_B_data_in_reg, V1_q_b[2]_PORT_A_address_reg, V1_q_b[2]_PORT_B_address_reg, V1_q_b[2]_PORT_A_write_enable_reg, V1_q_b[2]_PORT_B_write_enable_reg, , , V1_q_b[2]_clock_0, V1_q_b[2]_clock_1, , , , );
V1_q_b[4] = V1_q_b[2]_PORT_B_data_out[2];
--V1_q_b[3] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[3] at M4K_X11_Y7
V1_q_b[2]_PORT_A_data_in = BUS(D1_DOUT[2], D1_DOUT[3], D1_DOUT[4], D1_DOUT[7]);
V1_q_b[2]_PORT_A_data_in_reg = DFFE(V1_q_b[2]_PORT_A_data_in, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[2], W1_ram_rom_data_reg[3], W1_ram_rom_data_reg[4], W1_ram_rom_data_reg[7]);
V1_q_b[2]_PORT_B_data_in_reg = DFFE(V1_q_b[2]_PORT_B_data_in, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[2]_PORT_A_address_reg = DFFE(V1_q_b[2]_PORT_A_address, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[2]_PORT_B_address_reg = DFFE(V1_q_b[2]_PORT_B_address, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[2]_PORT_A_write_enable_reg = DFFE(V1_q_b[2]_PORT_A_write_enable, V1_q_b[2]_clock_0, , , );
V1_q_b[2]_PORT_B_write_enable = W1L3;
V1_q_b[2]_PORT_B_write_enable_reg = DFFE(V1_q_b[2]_PORT_B_write_enable, V1_q_b[2]_clock_1, , , );
V1_q_b[2]_clock_0 = GLOBAL(F1L55);
V1_q_b[2]_clock_1 = GLOBAL(A1L8);
V1_q_b[2]_PORT_B_data_out = MEMORY(V1_q_b[2]_PORT_A_data_in_reg, V1_q_b[2]_PORT_B_data_in_reg, V1_q_b[2]_PORT_A_address_reg, V1_q_b[2]_PORT_B_address_reg, V1_q_b[2]_PORT_A_write_enable_reg, V1_q_b[2]_PORT_B_write_enable_reg, , , V1_q_b[2]_clock_0, V1_q_b[2]_clock_1, , , , );
V1_q_b[3] = V1_q_b[2]_PORT_B_data_out[1];
--N1L21 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|Select~709 at LCCOMB_X10_Y6_N24
N1L21 = V1_q_a[6] & (V1_q_a[1] & V1_q_a[2] # !V1_q_a[0]) # !V1_q_a[6] & !V1_q_a[0] & (V1_q_a[1] # V1_q_a[2]);
--N1L22 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|Select~710 at LCCOMB_X10_Y6_N26
N1L22 = V1_q_a[7] & (N1L21 & N1L20 # !V1_q_a[0]) # !V1_q_a[7] & !V1_q_a[0] & (N1L21 # N1L20);
--N1L23 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|Select~711 at LCCOMB_X10_Y6_N12
N1L23 = N1_state.f_end_s # N1_state.f_ready_s & !N1L22;
--R1_xmit_done is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xmit_done at LCFF_X10_Y7_N11
R1_xmit_done = DFFEAS(R1L1, GLOBAL(Q1L40), RST, , , , , , );
--N1_framecnt[9] is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|framecnt[9] at LCFF_X9_Y8_N31
N1_framecnt[9] = DFFEAS(N1L142, GLOBAL(N1L92), !GLOBAL(N1L192), , , , , N1_framecnt[9], );
--N1L230 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|xdata[2]~20 at LCCOMB_X10_Y6_N22
N1L230 = R1_xmit_done & !N1_framecnt[9] & N1_state.f_ready_s;
--N1_state.f_start_s is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|state.f_start_s at LCFF_X10_Y6_N11
N1_state.f_start_s = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(Q1L40), RST, , , N1_next_state.f_start_s, , , VCC);
--N1L231 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|xdata[2]~79 at LCCOMB_X10_Y6_N10
N1L231 = N1L230 # !N1_state.f_ready_s & (N1_state.f_end_s # N1_state.f_start_s);
--R1L36 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|partoser~396 at LCCOMB_X10_Y7_N30
R1L36 = R1_xmit_cmd_p & !R1_state.x_idle;
--R1L4 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|next_state.x_start~30~64 at LCCOMB_X9_Y7_N26
R1L4 = R1L36 # R1_state.x_start & (!R1_xcnt16[0] # !B1L4);
--CB10_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2] at LCFF_X15_Y5_N9
CB10_Q[2] = AMPP_FUNCTION(A1L8, A1L22, L1L5, L1L44);
--FB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LCFF_X15_Y7_N11
FB1_state[3] = AMPP_FUNCTION(A1L8, FB1L19);
--FB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LCFF_X15_Y7_N1
FB1_state[4] = AMPP_FUNCTION(A1L8, FB1L20, A1L10);
--L1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LCFF_X15_Y7_N29
L1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L8, A1L19, FB1_state[0], FB1_state[12]);
--W1L13 is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|sld_mod_ram_rom:mgl_prim2|name_gen~33 at LCCOMB_X15_Y6_N26
W1L13 = AMPP_FUNCTION(FB1_state[3], L1_jtag_debug_mode_usr1, FB1_state[4]);
--X3_WORD_SR[0] is ROM3:inst14|altsyncram:altsyncram_component|altsyncram_uk61:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] at LCFF_X18_Y5_N13
X3_WORD_SR[0] = AMPP_FUNCTION(A1L8, X3L27, X3L23);
--CB4_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[1] at LCFF_X14_Y3_N27
CB4_Q[1] = AMPP_FUNCTION(A1L8, L1L40, L1L5, L1L48);
--CB4_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] at LCFF_X14_Y3_N9
CB4_Q[2] = AMPP_FUNCTION(A1L8, L1L41, L1L5, L1L48);
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