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--R1L95 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xcnt16[4]~70 at LCCOMB_X9_Y7_N16
R1L95 = R1_xcnt16[4] $ !R1L92;
--R1L54 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xbitcnt[0]~54 at LCCOMB_X10_Y7_N12
R1L54 = R1_xbitcnt[0] & (R1L3 $ GND) # !R1_xbitcnt[0] & !R1L3 & VCC;
--R1L56 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xbitcnt[0]~55 at LCCOMB_X10_Y7_N12
R1L56 = CARRY(R1_xbitcnt[0] & !R1L3);
--R1L59 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xbitcnt[1]~56 at LCCOMB_X10_Y7_N14
R1L59 = R1_xbitcnt[1] & !R1L56 # !R1_xbitcnt[1] & (R1L56 # GND);
--R1L61 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xbitcnt[1]~57 at LCCOMB_X10_Y7_N14
R1L61 = CARRY(!R1L56 # !R1_xbitcnt[1]);
--R1L64 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xbitcnt[2]~58 at LCCOMB_X10_Y7_N16
R1L64 = R1_xbitcnt[2] & (R1L61 $ GND) # !R1_xbitcnt[2] & !R1L61 & VCC;
--R1L66 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xbitcnt[2]~59 at LCCOMB_X10_Y7_N16
R1L66 = CARRY(R1_xbitcnt[2] & !R1L61);
--R1L69 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|xbitcnt[3]~60 at LCCOMB_X10_Y7_N18
R1L69 = R1L66 $ R1_xbitcnt[3];
--R1L2 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|next_state.x_idle~35~0 at LCCOMB_X10_Y7_N26
R1L2 = !R1_xmit_cmd_p & !R1_state.x_idle;
--Q1_bclk_t is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_baud:iBAUD|bclk_t at LCFF_X1_Y6_N21
Q1_bclk_t = DFFEAS(Q1L35, GLOBAL(B1L1), RST, , , , , , );
--R1_partoser[2] is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|partoser[2] at LCFF_X10_Y8_N3
R1_partoser[2] = DFFEAS(R1L31, GLOBAL(Q1L40), RST, , R1L17, , , , );
--N1_xdata[1] is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|xdata[1] at LCFF_X10_Y6_N15
N1_xdata[1] = DFFEAS(N1L7, GLOBAL(Q1L40), , , N1L231, , , , );
--R1L30 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|partoser~36 at LCCOMB_X10_Y8_N0
R1L30 = R1_xmit_cmd_p & (R1_state.x_idle & (R1_partoser[2]) # !R1_state.x_idle & N1_xdata[1]) # !R1_xmit_cmd_p & (R1_partoser[2]);
--N1_state.f_end_s is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|state.f_end_s at LCFF_X8_Y7_N19
N1_state.f_end_s = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(Q1L40), RST, , , N1_next_state.f_end_s, , , VCC);
--N1_state.f_ready_s is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|state.f_ready_s at LCFF_X10_Y6_N31
N1_state.f_ready_s = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(Q1L40), RST, , , N1_next_state.f_ready_s, , , VCC);
--N1L20 is KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|Select~708 at LCCOMB_X10_Y6_N18
N1L20 = V1_q_a[6] & V1_q_a[4] & V1_q_a[5] & V1_q_a[3] # !V1_q_a[6] & (V1_q_a[4] # V1_q_a[5] # V1_q_a[3]);
--V1_q_a[0] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[0] at M4K_X11_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_a[0]_PORT_A_data_in = BUS(D1_DOUT[0], D1_DOUT[1], D1_DOUT[5], D1_DOUT[6]);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[0], W1_ram_rom_data_reg[1], W1_ram_rom_data_reg[5], W1_ram_rom_data_reg[6]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = W1L3;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(F1L55);
V1_q_a[0]_clock_1 = GLOBAL(A1L8);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[0] = V1_q_a[0]_PORT_A_data_out[0];
--V1_q_b[0] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[0] at M4K_X11_Y6
V1_q_b[0]_PORT_A_data_in = BUS(D1_DOUT[0], D1_DOUT[1], D1_DOUT[5], D1_DOUT[6]);
V1_q_b[0]_PORT_A_data_in_reg = DFFE(V1_q_b[0]_PORT_A_data_in, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[0], W1_ram_rom_data_reg[1], W1_ram_rom_data_reg[5], W1_ram_rom_data_reg[6]);
V1_q_b[0]_PORT_B_data_in_reg = DFFE(V1_q_b[0]_PORT_B_data_in, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[0]_PORT_A_address_reg = DFFE(V1_q_b[0]_PORT_A_address, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[0]_PORT_B_address_reg = DFFE(V1_q_b[0]_PORT_B_address, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[0]_PORT_A_write_enable_reg = DFFE(V1_q_b[0]_PORT_A_write_enable, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_write_enable = W1L3;
V1_q_b[0]_PORT_B_write_enable_reg = DFFE(V1_q_b[0]_PORT_B_write_enable, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_clock_0 = GLOBAL(F1L55);
V1_q_b[0]_clock_1 = GLOBAL(A1L8);
V1_q_b[0]_PORT_B_data_out = MEMORY(V1_q_b[0]_PORT_A_data_in_reg, V1_q_b[0]_PORT_B_data_in_reg, V1_q_b[0]_PORT_A_address_reg, V1_q_b[0]_PORT_B_address_reg, V1_q_b[0]_PORT_A_write_enable_reg, V1_q_b[0]_PORT_B_write_enable_reg, , , V1_q_b[0]_clock_0, V1_q_b[0]_clock_1, , , , );
V1_q_b[0] = V1_q_b[0]_PORT_B_data_out[0];
--V1_q_a[6] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[6] at M4K_X11_Y6
V1_q_a[0]_PORT_A_data_in = BUS(D1_DOUT[0], D1_DOUT[1], D1_DOUT[5], D1_DOUT[6]);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[0], W1_ram_rom_data_reg[1], W1_ram_rom_data_reg[5], W1_ram_rom_data_reg[6]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = W1L3;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(F1L55);
V1_q_a[0]_clock_1 = GLOBAL(A1L8);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[6] = V1_q_a[0]_PORT_A_data_out[3];
--V1_q_a[5] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[5] at M4K_X11_Y6
V1_q_a[0]_PORT_A_data_in = BUS(D1_DOUT[0], D1_DOUT[1], D1_DOUT[5], D1_DOUT[6]);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[0], W1_ram_rom_data_reg[1], W1_ram_rom_data_reg[5], W1_ram_rom_data_reg[6]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = W1L3;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(F1L55);
V1_q_a[0]_clock_1 = GLOBAL(A1L8);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[5] = V1_q_a[0]_PORT_A_data_out[2];
--V1_q_a[1] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[1] at M4K_X11_Y6
V1_q_a[0]_PORT_A_data_in = BUS(D1_DOUT[0], D1_DOUT[1], D1_DOUT[5], D1_DOUT[6]);
V1_q_a[0]_PORT_A_data_in_reg = DFFE(V1_q_a[0]_PORT_A_data_in, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[0], W1_ram_rom_data_reg[1], W1_ram_rom_data_reg[5], W1_ram_rom_data_reg[6]);
V1_q_a[0]_PORT_B_data_in_reg = DFFE(V1_q_a[0]_PORT_B_data_in, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_a[0]_PORT_B_address_reg = DFFE(V1_q_a[0]_PORT_B_address, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_a[0]_PORT_A_write_enable_reg = DFFE(V1_q_a[0]_PORT_A_write_enable, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_PORT_B_write_enable = W1L3;
V1_q_a[0]_PORT_B_write_enable_reg = DFFE(V1_q_a[0]_PORT_B_write_enable, V1_q_a[0]_clock_1, , , );
V1_q_a[0]_clock_0 = GLOBAL(F1L55);
V1_q_a[0]_clock_1 = GLOBAL(A1L8);
V1_q_a[0]_PORT_A_data_out = MEMORY(V1_q_a[0]_PORT_A_data_in_reg, V1_q_a[0]_PORT_B_data_in_reg, V1_q_a[0]_PORT_A_address_reg, V1_q_a[0]_PORT_B_address_reg, V1_q_a[0]_PORT_A_write_enable_reg, V1_q_a[0]_PORT_B_write_enable_reg, , , V1_q_a[0]_clock_0, V1_q_a[0]_clock_1, , , , );
V1_q_a[1] = V1_q_a[0]_PORT_A_data_out[1];
--V1_q_b[6] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[6] at M4K_X11_Y6
V1_q_b[0]_PORT_A_data_in = BUS(D1_DOUT[0], D1_DOUT[1], D1_DOUT[5], D1_DOUT[6]);
V1_q_b[0]_PORT_A_data_in_reg = DFFE(V1_q_b[0]_PORT_A_data_in, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[0], W1_ram_rom_data_reg[1], W1_ram_rom_data_reg[5], W1_ram_rom_data_reg[6]);
V1_q_b[0]_PORT_B_data_in_reg = DFFE(V1_q_b[0]_PORT_B_data_in, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[0]_PORT_A_address_reg = DFFE(V1_q_b[0]_PORT_A_address, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[0]_PORT_B_address_reg = DFFE(V1_q_b[0]_PORT_B_address, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[0]_PORT_A_write_enable_reg = DFFE(V1_q_b[0]_PORT_A_write_enable, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_write_enable = W1L3;
V1_q_b[0]_PORT_B_write_enable_reg = DFFE(V1_q_b[0]_PORT_B_write_enable, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_clock_0 = GLOBAL(F1L55);
V1_q_b[0]_clock_1 = GLOBAL(A1L8);
V1_q_b[0]_PORT_B_data_out = MEMORY(V1_q_b[0]_PORT_A_data_in_reg, V1_q_b[0]_PORT_B_data_in_reg, V1_q_b[0]_PORT_A_address_reg, V1_q_b[0]_PORT_B_address_reg, V1_q_b[0]_PORT_A_write_enable_reg, V1_q_b[0]_PORT_B_write_enable_reg, , , V1_q_b[0]_clock_0, V1_q_b[0]_clock_1, , , , );
V1_q_b[6] = V1_q_b[0]_PORT_B_data_out[3];
--V1_q_b[5] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[5] at M4K_X11_Y6
V1_q_b[0]_PORT_A_data_in = BUS(D1_DOUT[0], D1_DOUT[1], D1_DOUT[5], D1_DOUT[6]);
V1_q_b[0]_PORT_A_data_in_reg = DFFE(V1_q_b[0]_PORT_A_data_in, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[0], W1_ram_rom_data_reg[1], W1_ram_rom_data_reg[5], W1_ram_rom_data_reg[6]);
V1_q_b[0]_PORT_B_data_in_reg = DFFE(V1_q_b[0]_PORT_B_data_in, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[0]_PORT_A_address_reg = DFFE(V1_q_b[0]_PORT_A_address, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[0]_PORT_B_address_reg = DFFE(V1_q_b[0]_PORT_B_address, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[0]_PORT_A_write_enable_reg = DFFE(V1_q_b[0]_PORT_A_write_enable, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_write_enable = W1L3;
V1_q_b[0]_PORT_B_write_enable_reg = DFFE(V1_q_b[0]_PORT_B_write_enable, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_clock_0 = GLOBAL(F1L55);
V1_q_b[0]_clock_1 = GLOBAL(A1L8);
V1_q_b[0]_PORT_B_data_out = MEMORY(V1_q_b[0]_PORT_A_data_in_reg, V1_q_b[0]_PORT_B_data_in_reg, V1_q_b[0]_PORT_A_address_reg, V1_q_b[0]_PORT_B_address_reg, V1_q_b[0]_PORT_A_write_enable_reg, V1_q_b[0]_PORT_B_write_enable_reg, , , V1_q_b[0]_clock_0, V1_q_b[0]_clock_1, , , , );
V1_q_b[5] = V1_q_b[0]_PORT_B_data_out[2];
--V1_q_b[1] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_b[1] at M4K_X11_Y6
V1_q_b[0]_PORT_A_data_in = BUS(D1_DOUT[0], D1_DOUT[1], D1_DOUT[5], D1_DOUT[6]);
V1_q_b[0]_PORT_A_data_in_reg = DFFE(V1_q_b[0]_PORT_A_data_in, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_data_in = BUS(W1_ram_rom_data_reg[0], W1_ram_rom_data_reg[1], W1_ram_rom_data_reg[5], W1_ram_rom_data_reg[6]);
V1_q_b[0]_PORT_B_data_in_reg = DFFE(V1_q_b[0]_PORT_B_data_in, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_address = BUS(F1_address[0], F1_address[1], F1_address[2], F1_address[3], F1_address[4], F1_address[5], F1_address[6], F1_address[7], F1_address[8], F1_address[9]);
V1_q_b[0]_PORT_A_address_reg = DFFE(V1_q_b[0]_PORT_A_address, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_address = BUS(W1_ram_rom_addr_reg[0], W1_ram_rom_addr_reg[1], W1_ram_rom_addr_reg[2], W1_ram_rom_addr_reg[3], W1_ram_rom_addr_reg[4], W1_ram_rom_addr_reg[5], W1_ram_rom_addr_reg[6], W1_ram_rom_addr_reg[7], W1_ram_rom_addr_reg[8], W1_ram_rom_addr_reg[9]);
V1_q_b[0]_PORT_B_address_reg = DFFE(V1_q_b[0]_PORT_B_address, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_write_enable = !F1_current1.st1;
V1_q_b[0]_PORT_A_write_enable_reg = DFFE(V1_q_b[0]_PORT_A_write_enable, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_write_enable = W1L3;
V1_q_b[0]_PORT_B_write_enable_reg = DFFE(V1_q_b[0]_PORT_B_write_enable, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_clock_0 = GLOBAL(F1L55);
V1_q_b[0]_clock_1 = GLOBAL(A1L8);
V1_q_b[0]_PORT_B_data_out = MEMORY(V1_q_b[0]_PORT_A_data_in_reg, V1_q_b[0]_PORT_B_data_in_reg, V1_q_b[0]_PORT_A_address_reg, V1_q_b[0]_PORT_B_address_reg, V1_q_b[0]_PORT_A_write_enable_reg, V1_q_b[0]_PORT_B_write_enable_reg, , , V1_q_b[0]_clock_0, V1_q_b[0]_clock_1, , , , );
V1_q_b[1] = V1_q_b[0]_PORT_B_data_out[1];
--V1_q_a[2] is LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|q_a[2] at M4K_X11_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
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