spc.tan.summary

Alera 的8051 IP core的示例文件5个

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.917 ns
From           : S1
To             : REG8B:inst6|DOUT[6]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.699 ns
From           : KX232:inst1|KONXIN1:inst1|KONXIN_EXP1:inst|suart:iUART|u_xmit:iXMIT|state.x_wait
To             : TXD
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 3.046 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.838 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'PLL20:inst4|altpll:altpll_component|_clk0'
Slack          : 16.002 ns
Required Time  : 12.00 MHz ( period = 83.333 ns )
Actual Time    : N/A
From           : REG8B:inst6|DOUT[0]
To             : LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|ram_block3a0~porta_datain_reg0
From Clock     : PLL20:inst4|altpll:altpll_component|_clk1
To Clock       : PLL20:inst4|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'PLL20:inst4|altpll:altpll_component|_clk1'
Slack          : 42.080 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : N/A
From           : CNT8B:inst10|Q1[5]
To             : ROMH:inst11|altsyncram:altsyncram_component|altsyncram_bj61:auto_generated|altsyncram_69a2:altsyncram1|ram_block3a0~porta_address_reg5
From Clock     : PLL20:inst4|altpll:altpll_component|_clk1
To Clock       : PLL20:inst4|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 90.63 MHz ( period = 11.034 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'PLL20:inst4|altpll:altpll_component|_clk0'
Slack          : -6.214 ns
Required Time  : 12.00 MHz ( period = 83.333 ns )
Actual Time    : N/A
From           : KXRAM:inst9|address[7]
To             : LPMRAM:inst8|altsyncram:altsyncram_component|altsyncram_7e91:auto_generated|altsyncram_ia92:altsyncram1|ram_block3a0~porta_address_reg7
From Clock     : PLL20:inst4|altpll:altpll_component|_clk0
To Clock       : PLL20:inst4|altpll:altpll_component|_clk0
Failed Paths   : 102

Type           : Clock Hold: 'PLL20:inst4|altpll:altpll_component|_clk1'
Slack          : 0.740 ns
Required Time  : 10.00 MHz ( period = 100.000 ns )
Actual Time    : N/A
From           : CNT8B:inst10|Q1[7]
To             : CNT8B:inst10|Q1[7]
From Clock     : PLL20:inst4|altpll:altpll_component|_clk1
To Clock       : PLL20:inst4|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 102

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