gray.tan.qmsg

来自「基于FPGA编写的VHDL语言」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "new_q\[1\] en clk -4.210 ns register " "Info: th for register \"new_q\[1\]\" (data pin = \"en\", clock pin = \"clk\") is -4.210 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.866 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.866 ns new_q\[1\] 3 REG LCFF_X1_Y3_N11 4 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N11; Fanout = 4; REG Node = 'new_q\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl new_q[1] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.01 % ) " "Info: Total cell delay = 1.806 ns ( 63.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 36.99 % ) " "Info: Total interconnect delay = 1.060 ns ( 36.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[1] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.382 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.382 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns en 1 PIN PIN_46 3 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_46; Fanout = 3; PIN Node = 'en'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.628 ns) + CELL(0.651 ns) 7.274 ns new_q\[1\]~825 2 COMB LCCOMB_X1_Y3_N10 1 " "Info: 2: + IC(5.628 ns) + CELL(0.651 ns) = 7.274 ns; Loc. = LCCOMB_X1_Y3_N10; Fanout = 1; COMB Node = 'new_q\[1\]~825'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.279 ns" { en new_q[1]~825 } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.382 ns new_q\[1\] 3 REG LCFF_X1_Y3_N11 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.382 ns; Loc. = LCFF_X1_Y3_N11; Fanout = 4; REG Node = 'new_q\[1\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { new_q[1]~825 new_q[1] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.754 ns ( 23.76 % ) " "Info: Total cell delay = 1.754 ns ( 23.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.628 ns ( 76.24 % ) " "Info: Total interconnect delay = 5.628 ns ( 76.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.382 ns" { en new_q[1]~825 new_q[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.382 ns" { en {} en~combout {} new_q[1]~825 {} new_q[1] {} } { 0.000ns 0.000ns 5.628ns 0.000ns } { 0.000ns 0.995ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[1] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.382 ns" { en new_q[1]~825 new_q[1] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.382 ns" { en {} en~combout {} new_q[1]~825 {} new_q[1] {} } { 0.000ns 0.000ns 5.628ns 0.000ns } { 0.000ns 0.995ns 0.651ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Peak virtual memory: 131 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 09 21:10:10 2009 " "Info: Processing ended: Thu Apr 09 21:10:10 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}