gray.tan.qmsg

来自「基于FPGA编写的VHDL语言」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } } { "d:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register new_q\[3\] new_q\[3\] 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"new_q\[3\]\" and destination register \"new_q\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.325 ns + Longest register register " "Info: + Longest register to register delay is 2.325 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns new_q\[3\] 1 REG LCFF_X1_Y3_N15 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { new_q[3] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.623 ns) 1.061 ns normal\[2\] 2 COMB LCCOMB_X1_Y3_N18 3 " "Info: 2: + IC(0.438 ns) + CELL(0.623 ns) = 1.061 ns; Loc. = LCCOMB_X1_Y3_N18; Fanout = 3; COMB Node = 'normal\[2\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.061 ns" { new_q[3] normal[2] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.206 ns) 1.638 ns new_q\[4\]~826 3 COMB LCCOMB_X1_Y3_N28 3 " "Info: 3: + IC(0.371 ns) + CELL(0.206 ns) = 1.638 ns; Loc. = LCCOMB_X1_Y3_N28; Fanout = 3; COMB Node = 'new_q\[4\]~826'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.577 ns" { normal[2] new_q[4]~826 } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.206 ns) 2.217 ns new_q\[3\]~828 4 COMB LCCOMB_X1_Y3_N14 1 " "Info: 4: + IC(0.373 ns) + CELL(0.206 ns) = 2.217 ns; Loc. = LCCOMB_X1_Y3_N14; Fanout = 1; COMB Node = 'new_q\[3\]~828'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.579 ns" { new_q[4]~826 new_q[3]~828 } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.325 ns new_q\[3\] 5 REG LCFF_X1_Y3_N15 5 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.325 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { new_q[3]~828 new_q[3] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.143 ns ( 49.16 % ) " "Info: Total cell delay = 1.143 ns ( 49.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.182 ns ( 50.84 % ) " "Info: Total interconnect delay = 1.182 ns ( 50.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.325 ns" { new_q[3] normal[2] new_q[4]~826 new_q[3]~828 new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.325 ns" { new_q[3] {} normal[2] {} new_q[4]~826 {} new_q[3]~828 {} new_q[3] {} } { 0.000ns 0.438ns 0.371ns 0.373ns 0.000ns } { 0.000ns 0.623ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.866 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.866 ns new_q\[3\] 3 REG LCFF_X1_Y3_N15 5 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl new_q[3] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.01 % ) " "Info: Total cell delay = 1.806 ns ( 63.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 36.99 % ) " "Info: Total interconnect delay = 1.060 ns ( 36.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.866 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.866 ns new_q\[3\] 3 REG LCFF_X1_Y3_N15 5 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl new_q[3] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.01 % ) " "Info: Total cell delay = 1.806 ns ( 63.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 36.99 % ) " "Info: Total interconnect delay = 1.060 ns ( 36.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.325 ns" { new_q[3] normal[2] new_q[4]~826 new_q[3]~828 new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.325 ns" { new_q[3] {} normal[2] {} new_q[4]~826 {} new_q[3]~828 {} new_q[3] {} } { 0.000ns 0.438ns 0.371ns 0.373ns 0.000ns } { 0.000ns 0.623ns 0.206ns 0.206ns 0.108ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { new_q[3] {} } {  } {  } "" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "new_q\[3\] en clk 5.365 ns register " "Info: tsu for register \"new_q\[3\]\" (data pin = \"en\", clock pin = \"clk\") is 5.365 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.271 ns + Longest pin register " "Info: + Longest pin to register delay is 8.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns en 1 PIN PIN_46 3 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_46; Fanout = 3; PIN Node = 'en'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.966 ns) + CELL(0.623 ns) 7.584 ns new_q\[4\]~826 2 COMB LCCOMB_X1_Y3_N28 3 " "Info: 2: + IC(5.966 ns) + CELL(0.623 ns) = 7.584 ns; Loc. = LCCOMB_X1_Y3_N28; Fanout = 3; COMB Node = 'new_q\[4\]~826'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.589 ns" { en new_q[4]~826 } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.206 ns) 8.163 ns new_q\[3\]~828 3 COMB LCCOMB_X1_Y3_N14 1 " "Info: 3: + IC(0.373 ns) + CELL(0.206 ns) = 8.163 ns; Loc. = LCCOMB_X1_Y3_N14; Fanout = 1; COMB Node = 'new_q\[3\]~828'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.579 ns" { new_q[4]~826 new_q[3]~828 } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.271 ns new_q\[3\] 4 REG LCFF_X1_Y3_N15 5 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 8.271 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { new_q[3]~828 new_q[3] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.932 ns ( 23.36 % ) " "Info: Total cell delay = 1.932 ns ( 23.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.339 ns ( 76.64 % ) " "Info: Total interconnect delay = 6.339 ns ( 76.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.271 ns" { en new_q[4]~826 new_q[3]~828 new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.271 ns" { en {} en~combout {} new_q[4]~826 {} new_q[3]~828 {} new_q[3] {} } { 0.000ns 0.000ns 5.966ns 0.373ns 0.000ns } { 0.000ns 0.995ns 0.623ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.866 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.866 ns new_q\[3\] 3 REG LCFF_X1_Y3_N15 5 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N15; Fanout = 5; REG Node = 'new_q\[3\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl new_q[3] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.01 % ) " "Info: Total cell delay = 1.806 ns ( 63.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 36.99 % ) " "Info: Total interconnect delay = 1.060 ns ( 36.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.271 ns" { en new_q[4]~826 new_q[3]~828 new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.271 ns" { en {} en~combout {} new_q[4]~826 {} new_q[3]~828 {} new_q[3] {} } { 0.000ns 0.000ns 5.966ns 0.373ns 0.000ns } { 0.000ns 0.995ns 0.623ns 0.206ns 0.108ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[3] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[3] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[0\] new_q\[0\] 8.583 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[0\]\" through register \"new_q\[0\]\" is 8.583 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.866 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.866 ns new_q\[0\] 3 REG LCFF_X1_Y3_N25 4 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.866 ns; Loc. = LCFF_X1_Y3_N25; Fanout = 4; REG Node = 'new_q\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl new_q[0] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.01 % ) " "Info: Total cell delay = 1.806 ns ( 63.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 36.99 % ) " "Info: Total interconnect delay = 1.060 ns ( 36.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[0] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.413 ns + Longest register pin " "Info: + Longest register to pin delay is 5.413 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns new_q\[0\] 1 REG LCFF_X1_Y3_N25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N25; Fanout = 4; REG Node = 'new_q\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { new_q[0] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.127 ns) + CELL(3.286 ns) 5.413 ns q\[0\] 2 PIN PIN_69 0 " "Info: 2: + IC(2.127 ns) + CELL(3.286 ns) = 5.413 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.413 ns" { new_q[0] q[0] } "NODE_NAME" } } { "gray.vhd" "" { Text "E:/workroom2/quartusIIex/fifotop/gray.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 60.71 % ) " "Info: Total cell delay = 3.286 ns ( 60.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.127 ns ( 39.29 % ) " "Info: Total interconnect delay = 2.127 ns ( 39.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.413 ns" { new_q[0] q[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "5.413 ns" { new_q[0] {} q[0] {} } { 0.000ns 2.127ns } { 0.000ns 3.286ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { clk clk~clkctrl new_q[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.866 ns" { clk {} clk~combout {} clk~clkctrl {} new_q[0] {} } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.413 ns" { new_q[0] q[0] } "NODE_NAME" } } { "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/81/quartus/bin/Technology_Viewer.qrui" "5.413 ns" { new_q[0] {} q[0] {} } { 0.000ns 2.127ns } { 0.000ns 3.286ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}