e-try.fit.eqn

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-- Copyright (C) 1991-2005 Altera Corporation
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_CS7279 is FPGA_7279:inst|CS7279 at LC_X43_Y18_N3
--operation mode is normal

B1_CS7279_lut_out = !B1_state.finish & (B1_state.start # B1_CS7279);
B1_CS7279 = DFFEAS(B1_CS7279_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1_CLK7279 is FPGA_7279:inst|CLK7279 at LC_X43_Y17_N3
--operation mode is normal

B1_CLK7279_lut_out = B1_CLK7279 & (B1_state.shift_key_high # !B1L74) # !B1L73;
B1_CLK7279 = DFFEAS(B1_CLK7279_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--C3_clk_tmp is div:inst6|clk_tmp at LC_X30_Y4_N7
--operation mode is normal

C3_clk_tmp_lut_out = C3_clk_tmp $ (C3L21 & SYS_RST_N);
C3_clk_tmp = DFFEAS(C3_clk_tmp_lut_out, !GLOBAL(SYS_CLK), VCC, , , , , , );


--C2_clk_tmp is div:inst1|clk_tmp at LC_X25_Y16_N2
--operation mode is normal

C2_clk_tmp_lut_out = C2_clk_tmp $ (SYS_RST_N & C2L28);
C2_clk_tmp = DFFEAS(C2_clk_tmp_lut_out, !GLOBAL(SYS_CLK), VCC, , , , , , );


--C1_clk_tmp is div:inst7|clk_tmp at LC_X28_Y12_N2
--operation mode is normal

C1_clk_tmp_lut_out = C1_clk_tmp $ (C1L79 & SYS_RST_N);
C1_clk_tmp = DFFEAS(C1_clk_tmp_lut_out, !GLOBAL(SYS_CLK), VCC, , , , , , );


--B1_key_7279[7] is FPGA_7279:inst|key_7279[7] at LC_X42_Y17_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_key_7279[7]_lut_out = GND;
B1_key_7279[7] = DFFEAS(B1_key_7279[7]_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L42, B1_key_7279_tmp[7], , , VCC);


--B1_key_7279[6] is FPGA_7279:inst|key_7279[6] at LC_X42_Y17_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_key_7279[6]_lut_out = GND;
B1_key_7279[6] = DFFEAS(B1_key_7279[6]_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L42, B1_key_7279_tmp[6], , , VCC);


--B1_key_7279[5] is FPGA_7279:inst|key_7279[5] at LC_X42_Y17_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_key_7279[5]_lut_out = GND;
B1_key_7279[5] = DFFEAS(B1_key_7279[5]_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L42, B1_key_7279_tmp[5], , , VCC);


--B1_key_7279[4] is FPGA_7279:inst|key_7279[4] at LC_X42_Y17_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_key_7279[4]_lut_out = GND;
B1_key_7279[4] = DFFEAS(B1_key_7279[4]_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L42, B1_key_7279_tmp[4], , , VCC);


--B1_key_7279[3] is FPGA_7279:inst|key_7279[3] at LC_X42_Y17_N1
--operation mode is normal

B1_key_7279[3]_lut_out = B1_key_7279_tmp[3];
B1_key_7279[3] = DFFEAS(B1_key_7279[3]_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L42, , , , );


--B1_key_7279[2] is FPGA_7279:inst|key_7279[2] at LC_X42_Y17_N5
--operation mode is normal

B1_key_7279[2]_lut_out = B1_key_7279_tmp[2];
B1_key_7279[2] = DFFEAS(B1_key_7279[2]_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L42, , , , );


--B1_key_7279[1] is FPGA_7279:inst|key_7279[1] at LC_X42_Y17_N6
--operation mode is normal

B1_key_7279[1]_lut_out = B1_key_7279_tmp[1];
B1_key_7279[1] = DFFEAS(B1_key_7279[1]_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L42, , , , );


--B1_key_7279[0] is FPGA_7279:inst|key_7279[0] at LC_X42_Y18_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_key_7279[0]_lut_out = GND;
B1_key_7279[0] = DFFEAS(B1_key_7279[0]_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L42, B1_key_7279_tmp[0], , , VCC);


--B1_state.finish is FPGA_7279:inst|state.finish at LC_X43_Y17_N2
--operation mode is normal

B1_state.finish_lut_out = B1L75 # B1L76 & !B1L54;
B1_state.finish = DFFEAS(B1_state.finish_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1_state.start is FPGA_7279:inst|state.start at LC_X43_Y18_N9
--operation mode is normal

B1_state.start_lut_out = !B1_state.idle;
B1_state.start = DFFEAS(B1_state.start_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1_state.shift_data_low is FPGA_7279:inst|state.shift_data_low at LC_X42_Y16_N0
--operation mode is normal

B1_state.shift_data_low_lut_out = B1L79 # B1_state.next_delay & !B1_delay_cnt[1] & !A1L22;
B1_state.shift_data_low = DFFEAS(B1_state.shift_data_low_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1_state.shift_key_low is FPGA_7279:inst|state.shift_key_low at LC_X42_Y16_N4
--operation mode is normal

B1_state.shift_key_low_lut_out = B1L81 # B1_state.next_delay & A1L22 & !B1_delay_cnt[1];
B1_state.shift_key_low = DFFEAS(B1_state.shift_key_low_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1L73 is FPGA_7279:inst|Select~1058 at LC_X44_Y17_N0
--operation mode is normal

B1L73 = !B1_state.shift_key_low & (!B1_state.shift_data_low & !B1_state.shift_cmd_low);


--B1_state.next_delay is FPGA_7279:inst|state.next_delay at LC_X43_Y16_N8
--operation mode is normal

B1_state.next_delay_lut_out = B1L76 & (B1L54 # B1_state.next_delay & B1_delay_cnt[1]) # !B1L76 & (B1_state.next_delay & B1_delay_cnt[1]);
B1_state.next_delay = DFFEAS(B1_state.next_delay_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1_state.start_delay is FPGA_7279:inst|state.start_delay at LC_X44_Y16_N3
--operation mode is normal

B1_state.start_delay_lut_out = B1_state.start # B1_delay_cnt[1] & (B1_state.start_delay);
B1_state.start_delay = DFFEAS(B1_state.start_delay_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1_state.idle is FPGA_7279:inst|state.idle at LC_X43_Y17_N4
--operation mode is normal

B1_state.idle_lut_out = !B1_state.finish;
B1_state.idle = DFFEAS(B1_state.idle_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1L74 is FPGA_7279:inst|Select~1059 at LC_X43_Y17_N1
--operation mode is normal

B1L74 = !B1_state.start_delay & B1_state.idle & !B1_state.finish & !B1_state.next_delay;


--C3_fre_N[0] is div:inst6|fre_N[0] at LC_X30_Y4_N1
--operation mode is arithmetic

C3_fre_N[0]_lut_out = !C3_fre_N[0];
C3_fre_N[0] = DFFEAS(C3_fre_N[0]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C3L21, );

--C3L4 is div:inst6|fre_N[0]~124 at LC_X30_Y4_N1
--operation mode is arithmetic

C3L4_cout_0 = C3_fre_N[0];
C3L4 = CARRY(C3L4_cout_0);

--C3L5 is div:inst6|fre_N[0]~124COUT1_149 at LC_X30_Y4_N1
--operation mode is arithmetic

C3L5_cout_1 = C3_fre_N[0];
C3L5 = CARRY(C3L5_cout_1);


--C3_fre_N[1] is div:inst6|fre_N[1] at LC_X30_Y4_N2
--operation mode is arithmetic

C3_fre_N[1]_lut_out = C3_fre_N[1] $ (C3L4);
C3_fre_N[1] = DFFEAS(C3_fre_N[1]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C3L21, );

--C3L7 is div:inst6|fre_N[1]~128 at LC_X30_Y4_N2
--operation mode is arithmetic

C3L7_cout_0 = !C3L4 # !C3_fre_N[1];
C3L7 = CARRY(C3L7_cout_0);

--C3L8 is div:inst6|fre_N[1]~128COUT1_150 at LC_X30_Y4_N2
--operation mode is arithmetic

C3L8_cout_1 = !C3L5 # !C3_fre_N[1];
C3L8 = CARRY(C3L8_cout_1);


--C3_fre_N[2] is div:inst6|fre_N[2] at LC_X30_Y4_N3
--operation mode is arithmetic

C3_fre_N[2]_lut_out = C3_fre_N[2] $ !C3L7;
C3_fre_N[2] = DFFEAS(C3_fre_N[2]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C3L21, );

--C3L10 is div:inst6|fre_N[2]~132 at LC_X30_Y4_N3
--operation mode is arithmetic

C3L10_cout_0 = C3_fre_N[2] & !C3L7;
C3L10 = CARRY(C3L10_cout_0);

--C3L11 is div:inst6|fre_N[2]~132COUT1 at LC_X30_Y4_N3
--operation mode is arithmetic

C3L11_cout_1 = C3_fre_N[2] & !C3L8;
C3L11 = CARRY(C3L11_cout_1);


--C3_fre_N[3] is div:inst6|fre_N[3] at LC_X30_Y4_N4
--operation mode is arithmetic

C3_fre_N[3]_lut_out = C3_fre_N[3] $ C3L10;
C3_fre_N[3] = DFFEAS(C3_fre_N[3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C3L21, );

--C3L13 is div:inst6|fre_N[3]~136 at LC_X30_Y4_N4
--operation mode is arithmetic

C3L13 = C3L14;


--C3L16 is div:inst6|fre_N[3]~139 at LC_X30_Y4_N9
--operation mode is normal

C3L16 = !C3_fre_N[0] & !C3_fre_N[3] & !C3_fre_N[1] & !C3_fre_N[2];


--C3_fre_N[4] is div:inst6|fre_N[4] at LC_X30_Y4_N5
--operation mode is arithmetic

C3_fre_N[4]_carry_eqn = (!C3L13 & GND) # (C3L13 & VCC);
C3_fre_N[4]_lut_out = C3_fre_N[4] $ !C3_fre_N[4]_carry_eqn;
C3_fre_N[4] = DFFEAS(C3_fre_N[4]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C3L21, );

--C3L18 is div:inst6|fre_N[4]~141 at LC_X30_Y4_N5
--operation mode is arithmetic

C3L18_cout_0 = C3_fre_N[4] & !C3L13;
C3L18 = CARRY(C3L18_cout_0);

--C3L19 is div:inst6|fre_N[4]~141COUT1_151 at LC_X30_Y4_N5
--operation mode is arithmetic

C3L19_cout_1 = C3_fre_N[4] & !C3L13;
C3L19 = CARRY(C3L19_cout_1);


--C3_fre_N[5] is div:inst6|fre_N[5] at LC_X30_Y4_N6
--operation mode is normal

C3_fre_N[5]_carry_eqn = (!C3L13 & C3L18) # (C3L13 & C3L19);
C3_fre_N[5]_lut_out = C3_fre_N[5]_carry_eqn $ C3_fre_N[5];
C3_fre_N[5] = DFFEAS(C3_fre_N[5]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C3L21, );


--C3L21 is div:inst6|LessThan~65 at LC_X30_Y4_N8
--operation mode is normal

C3L21 = C3_fre_N[5] & C3_fre_N[4] & !C3L16;


--C2_fre_N[0] is div:inst1|fre_N[0] at LC_X37_Y16_N0
--operation mode is arithmetic

C2_fre_N[0]_lut_out = !C2_fre_N[0];
C2_fre_N[0] = DFFEAS(C2_fre_N[0]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C2L28, );

--C2L4 is div:inst1|fre_N[0]~120 at LC_X37_Y16_N0
--operation mode is arithmetic

C2L4_cout_0 = C2_fre_N[0];
C2L4 = CARRY(C2L4_cout_0);

--C2L5 is div:inst1|fre_N[0]~120COUT1_152 at LC_X37_Y16_N0
--operation mode is arithmetic

C2L5_cout_1 = C2_fre_N[0];
C2L5 = CARRY(C2L5_cout_1);


--C2_fre_N[1] is div:inst1|fre_N[1] at LC_X37_Y16_N1
--operation mode is arithmetic

C2_fre_N[1]_lut_out = C2_fre_N[1] $ (C2L4);
C2_fre_N[1] = DFFEAS(C2_fre_N[1]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C2L28, );

--C2L7 is div:inst1|fre_N[1]~124 at LC_X37_Y16_N1
--operation mode is arithmetic

C2L7_cout_0 = !C2L4 # !C2_fre_N[1];
C2L7 = CARRY(C2L7_cout_0);

--C2L8 is div:inst1|fre_N[1]~124COUT1_153 at LC_X37_Y16_N1
--operation mode is arithmetic

C2L8_cout_1 = !C2L5 # !C2_fre_N[1];
C2L8 = CARRY(C2L8_cout_1);


--C2_fre_N[2] is div:inst1|fre_N[2] at LC_X37_Y16_N2
--operation mode is arithmetic

C2_fre_N[2]_lut_out = C2_fre_N[2] $ (!C2L7);
C2_fre_N[2] = DFFEAS(C2_fre_N[2]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C2L28, );

--C2L10 is div:inst1|fre_N[2]~128 at LC_X37_Y16_N2
--operation mode is arithmetic

C2L10_cout_0 = C2_fre_N[2] & (!C2L7);
C2L10 = CARRY(C2L10_cout_0);

--C2L11 is div:inst1|fre_N[2]~128COUT1_154 at LC_X37_Y16_N2
--operation mode is arithmetic

C2L11_cout_1 = C2_fre_N[2] & (!C2L8);
C2L11 = CARRY(C2L11_cout_1);


--C2_fre_N[3] is div:inst1|fre_N[3] at LC_X37_Y16_N3
--operation mode is arithmetic

C2_fre_N[3]_lut_out = C2_fre_N[3] $ C2L10;
C2_fre_N[3] = DFFEAS(C2_fre_N[3]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C2L28, );

--C2L13 is div:inst1|fre_N[3]~132 at LC_X37_Y16_N3
--operation mode is arithmetic

C2L13_cout_0 = !C2L10 # !C2_fre_N[3];
C2L13 = CARRY(C2L13_cout_0);

--C2L14 is div:inst1|fre_N[3]~132COUT1 at LC_X37_Y16_N3
--operation mode is arithmetic

C2L14_cout_1 = !C2L11 # !C2_fre_N[3];
C2L14 = CARRY(C2L14_cout_1);


--C2L26 is div:inst1|LessThan~118 at LC_X37_Y16_N9
--operation mode is normal

C2L26 = !C2_fre_N[3] & (!C2_fre_N[2] # !C2_fre_N[0] # !C2_fre_N[1]);


--C2_fre_N[4] is div:inst1|fre_N[4] at LC_X37_Y16_N4
--operation mode is arithmetic

C2_fre_N[4]_lut_out = C2_fre_N[4] $ !C2L13;
C2_fre_N[4] = DFFEAS(C2_fre_N[4]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C2L28, );

--C2L16 is div:inst1|fre_N[4]~136 at LC_X37_Y16_N4
--operation mode is arithmetic

C2L16 = C2L17;


--C2_fre_N[5] is div:inst1|fre_N[5] at LC_X37_Y16_N5
--operation mode is arithmetic

C2_fre_N[5]_carry_eqn = (!C2L16 & GND) # (C2L16 & VCC);
C2_fre_N[5]_lut_out = C2_fre_N[5] $ C2_fre_N[5]_carry_eqn;
C2_fre_N[5] = DFFEAS(C2_fre_N[5]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C2L28, );

--C2L20 is div:inst1|fre_N[5]~140 at LC_X37_Y16_N5
--operation mode is arithmetic

C2L20_cout_0 = !C2L16 # !C2_fre_N[5];
C2L20 = CARRY(C2L20_cout_0);

--C2L21 is div:inst1|fre_N[5]~140COUT1_155 at LC_X37_Y16_N5
--operation mode is arithmetic