e-try.fit.eqn

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--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp[7] = DFFEAS(A1L22, !GLOBAL(C2_clk_tmp), VCC, , B1L12, KEY7279, , , VCC);


--B1L81 is FPGA_7279:inst|Select~1068 at LC_X43_Y16_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_state.shift_key_high1_qfbk = B1_state.shift_key_high1;
B1L81 = B1_state.shift_key_high1_qfbk & (B1_sdata_cnt[1] # B1_sdata_cnt[2] # B1_sdata_cnt[0]);

--B1_state.shift_key_high1 is FPGA_7279:inst|state.shift_key_high1 at LC_X43_Y16_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_state.shift_key_high1 = DFFEAS(B1L81, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , B1_state.shift_key_high, , , VCC);


--B1L18 is FPGA_7279:inst|Decoder~106 at LC_X42_Y18_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_state.shift_key_high_qfbk = B1_state.shift_key_high;
B1L18 = B1_state.shift_key_high_qfbk & SYS_RST_N;

--B1_state.shift_key_high is FPGA_7279:inst|state.shift_key_high at LC_X42_Y18_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_state.shift_key_high = DFFEAS(B1L18, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , B1_state.shift_key_low, , , VCC);


--B1L19 is FPGA_7279:inst|Decoder~107 at LC_X42_Y18_N5
--operation mode is normal

B1L19 = B1_sdata_cnt[1] & B1_sdata_cnt[0] & B1_sdata_cnt[2] & B1L18;


--B1L67 is FPGA_7279:inst|sdata_cnt[2]~426 at LC_X43_Y16_N6
--operation mode is normal

B1L67 = SYS_RST_N & (B1L81 # B1L79 # B1L80);


--B1L20 is FPGA_7279:inst|Decoder~108 at LC_X42_Y18_N1
--operation mode is normal

B1L20 = B1_sdata_cnt[1] & !B1_sdata_cnt[0] & B1_sdata_cnt[2] & B1L18;


--B1L21 is FPGA_7279:inst|Decoder~109 at LC_X42_Y18_N9
--operation mode is normal

B1L21 = !B1_sdata_cnt[1] & B1_sdata_cnt[0] & B1_sdata_cnt[2] & B1L18;


--B1L22 is FPGA_7279:inst|Decoder~110 at LC_X41_Y17_N3
--operation mode is normal

B1L22 = !B1_sdata_cnt[0] & B1_sdata_cnt[2] & B1L18 & !B1_sdata_cnt[1];


--B1L23 is FPGA_7279:inst|Decoder~111 at LC_X41_Y17_N4
--operation mode is normal

B1L23 = B1_sdata_cnt[0] & !B1_sdata_cnt[2] & B1L18 & B1_sdata_cnt[1];


--B1L24 is FPGA_7279:inst|Decoder~112 at LC_X41_Y17_N6
--operation mode is normal

B1L24 = !B1_sdata_cnt[0] & !B1_sdata_cnt[2] & B1L18 & B1_sdata_cnt[1];


--B1L25 is FPGA_7279:inst|Decoder~113 at LC_X41_Y17_N5
--operation mode is normal

B1L25 = B1_sdata_cnt[0] & !B1_sdata_cnt[2] & B1L18 & !B1_sdata_cnt[1];


--B1L26 is FPGA_7279:inst|Decoder~114 at LC_X42_Y18_N2
--operation mode is normal

B1L26 = !B1_sdata_cnt[1] & !B1_sdata_cnt[0] & !B1_sdata_cnt[2] & B1L18;


--B1L14Q is FPGA_7279:inst|DAT7279~reg0 at LC_X44_Y17_N4
--operation mode is normal

B1L14Q_lut_out = !B1_state.shift_data_low & (B1L85 # B1L82 & !B1_scmd_cnt[0]);
B1L14Q = DFFEAS(B1L14Q_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L83, , , , );


--B1L55Q is FPGA_7279:inst|process0~1 at LC_X44_Y17_N6
--operation mode is normal

B1L55Q_lut_out = B1_state.idle & (!B1_state.shift_key_low);
B1L55Q = DFFEAS(B1L55Q_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , B1L83, , , , );


--B1L62 is FPGA_7279:inst|scmd_cnt[2]~333 at LC_X44_Y16_N1
--operation mode is normal

B1L62 = SYS_RST_N & (B1L78);


--B1_data_start is FPGA_7279:inst|data_start at LC_X43_Y18_N7
--operation mode is normal

B1_data_start_lut_out = B1_state.idle & B1_data_start # !B1_state.idle & (KEY7279);
B1_data_start = DFFEAS(B1_data_start_lut_out, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1L17 is FPGA_7279:inst|data_start_tmp~0 at LC_X44_Y17_N7
--operation mode is normal

B1L17 = B1_state.start & (SYS_RST_N);


--B1_delay_cnt[0] is FPGA_7279:inst|delay_cnt[0] at LC_X43_Y16_N3
--operation mode is normal

B1_delay_cnt[0]_lut_out = B1_delay_cnt[0] & (B1_state.shift_cmd_high # B1_state.start # !B1L32) # !B1_delay_cnt[0] & (B1L32);
B1_delay_cnt[0] = DFFEAS(B1_delay_cnt[0]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1L56 is FPGA_7279:inst|reduce_or~52 at LC_X43_Y16_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_state.shift_cmd_high_qfbk = B1_state.shift_cmd_high;
B1L56 = B1_state.start # B1_state.next_delay # B1_state.shift_cmd_high_qfbk # B1_state.start_delay;

--B1_state.shift_cmd_high is FPGA_7279:inst|state.shift_cmd_high at LC_X43_Y16_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_state.shift_cmd_high = DFFEAS(B1L56, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , B1_state.shift_cmd_low, , , VCC);


--B1L30 is FPGA_7279:inst|delay_cnt[1]~779 at LC_X43_Y16_N7
--operation mode is normal

B1L30 = !B1L80 & B1L56 & !B1L77 & SYS_RST_N;


--B1L31 is FPGA_7279:inst|delay_cnt[1]~780 at LC_X44_Y15_N2
--operation mode is normal

B1L31 = !B1_scmd_cnt[2] & !B1_scmd_cnt[1] & !B1_scmd_cnt[0];


--B1L32 is FPGA_7279:inst|delay_cnt[1]~781 at LC_X44_Y16_N8
--operation mode is normal

B1L32 = B1L30 & (B1L54 & B1L31 # !B1_state.shift_cmd_high);


--B1L57 is FPGA_7279:inst|reduce_or~53 at LC_X43_Y18_N4
--operation mode is normal

B1L57 = !B1_state.shift_cmd_high & !B1_state.start;


--B1_seg_cnt[2] is FPGA_7279:inst|seg_cnt[2] at LC_X43_Y18_N2
--operation mode is normal

B1_seg_cnt[2]_lut_out = B1_seg_cnt[2] $ (B1_seg_cnt[0] & B1L72 & B1_seg_cnt[1]);
B1_seg_cnt[2] = DFFEAS(B1_seg_cnt[2]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1L12 is FPGA_7279:inst|cmd_tmp[7]~46 at LC_X43_Y17_N9
--operation mode is normal

B1L12 = SYS_RST_N & (!B1_state.idle);


--B1_seg_cnt[0] is FPGA_7279:inst|seg_cnt[0] at LC_X43_Y18_N5
--operation mode is normal

B1_seg_cnt[0]_lut_out = B1_seg_cnt[0] $ (!B1_state.idle & KEY7279 & SYS_RST_N);
B1_seg_cnt[0] = DFFEAS(B1_seg_cnt[0]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_seg_cnt[1] is FPGA_7279:inst|seg_cnt[1] at LC_X43_Y18_N1
--operation mode is normal

B1_seg_cnt[1]_lut_out = B1_seg_cnt[1] $ (B1_seg_cnt[0] & B1L72);
B1_seg_cnt[1] = DFFEAS(B1_seg_cnt[1]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1L82 is FPGA_7279:inst|Select~1075 at LC_X44_Y17_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp1[0]_qfbk = B1_cmd_tmp1[0];
B1L82 = !B1_scmd_cnt[2] & (B1_scmd_cnt[1] & (B1_cmd_tmp1[2]) # !B1_scmd_cnt[1] & B1_cmd_tmp1[0]_qfbk);

--B1_cmd_tmp1[0] is FPGA_7279:inst|cmd_tmp1[0] at LC_X44_Y17_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp1[0] = DFFEAS(B1L82, !GLOBAL(C2_clk_tmp), VCC, , B1L17, B1_cmd_tmp[0], , , VCC);


--B1L83 is FPGA_7279:inst|Select~1077 at LC_X44_Y17_N8
--operation mode is normal

B1L83 = B1_state.idle & (!B1L73) # !B1_state.idle & !KEY7279;


--B1L72 is FPGA_7279:inst|seg_cnt[2]~3 at LC_X43_Y17_N6
--operation mode is normal

B1L72 = SYS_RST_N & KEY7279 & !B1_state.idle;


--B1L84 is FPGA_7279:inst|Select~1081 at LC_X44_Y17_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp1[1]_qfbk = B1_cmd_tmp1[1];
B1L84 = B1_scmd_cnt[2] & (B1_scmd_cnt[1] $ (!B1_scmd_cnt[0])) # !B1_scmd_cnt[2] & !B1_scmd_cnt[1] & B1_cmd_tmp1[1]_qfbk & B1_scmd_cnt[0];

--B1_cmd_tmp1[1] is FPGA_7279:inst|cmd_tmp1[1] at LC_X44_Y17_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp1[1] = DFFEAS(B1L84, !GLOBAL(C2_clk_tmp), VCC, , B1L17, B1_cmd_tmp[1], , , VCC);


--B1L85 is FPGA_7279:inst|Select~1082 at LC_X44_Y17_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp1[7]_qfbk = B1_cmd_tmp1[7];
B1L85 = B1L84 & (B1_cmd_tmp1[7]_qfbk # !B1_scmd_cnt[1]);

--B1_cmd_tmp1[7] is FPGA_7279:inst|cmd_tmp1[7] at LC_X44_Y17_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp1[7] = DFFEAS(B1L85, !GLOBAL(C2_clk_tmp), VCC, , B1L17, B1_cmd_tmp[7], , , VCC);


--tclk is tclk at PIN_86
--operation mode is input

tclk = INPUT();


--SYS_RST_N is SYS_RST_N at PIN_131
--operation mode is input

SYS_RST_N = INPUT();


--SYS_CLK is SYS_CLK at PIN_153
--operation mode is input

SYS_CLK = INPUT();


--KEY7279 is KEY7279 at PIN_159
--operation mode is input

KEY7279 = INPUT();


--CS_8019 is CS_8019 at PIN_141
--operation mode is output

CS_8019 = OUTPUT(VCC);


--KEY_EN is KEY_EN at PIN_108
--operation mode is output

KEY_EN = OUTPUT(GND);


--CS7279 is CS7279 at PIN_132
--operation mode is output

CS7279 = OUTPUT(!B1_CS7279);


--CLK7279 is CLK7279 at PIN_156
--operation mode is output

CLK7279 = OUTPUT(B1_CLK7279);


--AD_CLK500K is AD_CLK500K at PIN_98
--operation mode is output

AD_CLK500K = OUTPUT(C3_clk_tmp);


--CLK16us is CLK16us at PIN_23
--operation mode is output

CLK16us = OUTPUT(C2_clk_tmp);


--start1 is start1 at PIN_88
--operation mode is output

start1 = OUTPUT(GND);


--aa is aa at PIN_94
--operation mode is output

aa = OUTPUT(C1_clk_tmp);


--ena is ena at PIN_83
--operation mode is output

ena = OUTPUT(GND);


--OUT7279[7] is OUT7279[7] at PIN_161
--operation mode is output

OUT7279[7] = OUTPUT(B1_key_7279[7]);


--OUT7279[6] is OUT7279[6] at PIN_105
--operation mode is output

OUT7279[6] = OUTPUT(B1_key_7279[6]);


--OUT7279[5] is OUT7279[5] at PIN_197
--operation mode is output

OUT7279[5] = OUTPUT(B1_key_7279[5]);


--OUT7279[4] is OUT7279[4] at PIN_104
--operation mode is output

OUT7279[4] = OUTPUT(B1_key_7279[4]);


--OUT7279[3] is OUT7279[3] at PIN_168
--operation mode is output

OUT7279[3] = OUTPUT(B1_key_7279[3]);


--OUT7279[2] is OUT7279[2] at PIN_167
--operation mode is output

OUT7279[2] = OUTPUT(B1_key_7279[2]);


--OUT7279[1] is OUT7279[1] at PIN_166
--operation mode is output

OUT7279[1] = OUTPUT(B1_key_7279[1]);


--OUT7279[0] is OUT7279[0] at PIN_165
--operation mode is output

OUT7279[0] = OUTPUT(B1_key_7279[0]);


--A1L8 is DAT7279~0 at PIN_158
--operation mode is bidir

A1L8 = DAT7279;

--DAT7279 is DAT7279 at PIN_158
--operation mode is bidir

DAT7279_tri_out = TRI(B1L14Q, B1L55Q);
DAT7279 = BIDIR(DAT7279_tri_out);